Attorney’s Docket Number: USP-NT989
Filing Date: 3/12/2025
Claimed Priority Date: 11/14/2022 (CON of Parent App 17/986,314)
Inventor: Huang
Examiner: Thomas McCoy
DETAILED ACTION
This Office action responds to the application filed on 03/12/2025.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for a rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Objections
Claims 2-6 are objected to because of the following informalities: the “…a semiconductor device of claim 1…” recitation is improper, as “…a semiconductor device” was already introduced within the independent claim 1. For the purposes of examination, “…a semiconductor device of claim 1…” recitations of claims 2-6 will be construed to recite “…the semiconductor device of claim 1”. Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 3-4 are rejected under 35 U.S.C. 103 as being unpatentable over Shih (US 20210287937 A1).
Regarding claim 1, Shih (see, e.g., fig. 3) shows most aspects of the instant invention including a method for preparing a semiconductor device (e.g., semiconductor device 10C) comprising:
Forming an interconnect structure (e.g., left conductive layer 207 + right side conductive layer 207) disposed over a semiconductor substrate (e.g., semiconductor substrate 101), wherein the interconnect structure (e.g., left conductive layer 207 + right side conductive layer 207) comprises a first interconnect portion (e.g., left conductive layer 207) and a second interconnect portion (e.g., right conductive layer 207);
Forming a dielectric layer (e.g., plurality of first bottom liners 209 + paragraph 65 + plurality of first top liners 211 + paragraph 64) over the semiconductor substrate (e.g., semiconductor substrate 101) and covering the interconnect structure (e.g., left conductive layer 207 + right side conductive layer 207);
Forming a first opening (see, e.g., liner opening in the manufacturing step of fig. 11) penetrating through the dielectric layer (e.g., plurality of first bottom liners 209 + paragraph 65 + plurality of first top liners 211 + paragraph 64), wherein the first opening is between the first interconnect portion (e.g., left conductive layer 207) and the second interconnect portion (e.g., right conductive layer 207) of the interconnect structure (e.g., left conductive layer 207 + right side conductive layer 207);
Filling the first opening with a first porous dielectric portion (e.g., first porous layer 213);
forming a bonding pad (e.g., under bump metallization layer 411 + redistribution layer 409) over the dielectric layer (e.g., plurality of first bottom liners 209 + paragraph 65 + plurality of first top liners 211 + paragraph 64) and the first porous dielectric portion (e.g., first porous layer 213);
forming a first air gap (e.g., air gap within second porous layer 513) between the first porous dielectric portion (e.g., first porous layer 213) and the bonding pad (e.g., under bump metallization layer 411 + redistribution layer 409).
The current embodiment of Shih (see, e.g., fig. 3), however, fails to explicitly show performing a heat treatment process to form the first air gap between the first porous dielectric portion and the bonding pad.
However, Shih (see, e.g., fig. 18) teaches performing a heat treatment process (e.g., energy treatment of paragraph 95 “The energy treatment process may be performed on the intermediate semiconductor device in FIG. 18 by applying the energy source thereto. The energy source may include heat…”) to form an air gap (see, e.g., paragraph 62 “…first porous layers 213 may be regarded as air gaps…” + paragraph 95 “When heat is used as the energy source, a temperature of the energy treatment may be between about 800° C. and about 900° C. When light is used as the energy source, an ultraviolet light may be applied. The energy treatment may remove the decomposable porogen material from the energy-removable material to generate empty spaces (pores)”).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the heat treatment process of the first porous layer of Shih to form the second porous layer of the current embodiment of Shih, as heat treatment was a well-known method at the time of filing the invention to form a porous/air-gap layer, as taught by Shih (see, e.g., paragraph of Shih).
Regarding claim 3, Shih (see, e.g., fig. 3) shows wherein the bonding pad (e.g., under bump metallization layer 411 + redistribution layer 409) is separated from the first porous dielectric portion (e.g., porous layer 213) by the first air gap (e.g., air gap within second porous layer 513) after the heat treatment process is performed (see, e.g., rejection of claim 1, noting that the air gaps within second porous layer 513 are between the bonding pad and the first porous dielectric portion).
Regarding claim 4, Shih (see, e.g., fig. 3) shows wherein before the bonding pad (e.g., under bump metallization layer 411 + redistribution layer 409) is formed, the method further comprises: forming a second opening (see, e.g., paragraph 61 “…a plurality of first porous layers 213 may be respectively correspondingly disposed…only one first porous layer 213 is shown for clarity…”) in the dielectric layer (e.g., plurality of first bottom liners 209 + paragraph 65 + plurality of first top liners 211 + paragraph 64) to partially expose (see, e.g., manufacturing steps of figs. 11-18, note the dielectric layer has openings formed in both the interconnect regions and the porous layer regions) the first interconnect portion (e.g., left conductive layer 207) of the interconnect structure (e.g., left conductive layer 207 + right side conductive layer 207), filling the second opening (see, e.g., paragraph 61 “…a plurality of first porous layers 213 may be respectively correspondingly disposed…only one first porous layer 213 is shown for clarity…”) with a second porous dielectric portion (see, e.g., paragraph 61 “…a plurality of first porous layers 213 may be respectively correspondingly disposed…only one first porous layer 213 is shown for clarity…”), wherein the second porous dielectric portion and the first porous dielectric portion (e.g., first porous layer 213) comprise a porous low-k dielectric material (see, e.g., paragraph 62 “The plurality of first porous layers 213 may be formed from an energy-removable material. Each of the plurality of first porous layers 213 may include a skeleton and a plurality of empty spaces disposed among the skeleton. The plurality of empty spaces may be connected to each other and may be filled with air. The skeleton may include, for example, silicon oxide, low-dielectric materials”).
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Shih (US 20210287937 A1) in view of Chang (US 20150001710 A1).
Regarding claim 7, Shih (see, e.g., fig. 3N) shows forming a passivation layer (e.g., top passivation layer 403) covering the bonding pad (e.g., under bump metallization layer 411 + redistribution layer 409), forming a third opening in the passivation layer (e.g., top passivation layer 403) to expose a portion of the bonding pad (e.g., under bump metallization layer 411 + redistribution layer 409), wherein the portion of the bonding pad (e.g., under bump metallization layer 411 + redistribution layer 409) exposed by the third opening overlaps the first air gap (e.g., air gap within second porous layer 513) in a top view.
Shih (see, e.g., fig. 3), however, fails to show performing a bonding process to attach a wire bond to the bonding pad through the third opening, wherein a protruding portion extending toward the first porous dielectric portion is formed after the bonding process is performed.
Chang (see, e.g., fig. 5), in a similar device to Shih, teaches performing a bonding process (see, e.g., paragraph 53) to attach a wire bond (e.g., wire bond 135) to a bonding pad (e.g., conductive pad 112a) through an opening (e.g., second opening 112).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the bonding process of Chang within the bonding pad/opening arrangement of Shih, in order to achieve the expected result of providing a protruding conductive interface attached to the bonding pad that extends to other regions of the device as desired. Note that the protruding portion of this bond wire would extend toward the first porous dielectric portion, as the wire bond extends both toward and away from the bonding pad, which is configured above the first porous dielectric portion.
Allowable Subject Matter
Claims 2 and 5-6 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 2: the primary art of record, Shih (US 20210287937 A1) fails to show wherein the bonding pad is in direct contact with the first porous dielectric portion before the heat treatment process is performed. These features in combination with other elements in the claim are neither disclosed nor suggested by the prior art of record.
Regarding claim 5, the primary art of record, Shih (US 20210287937 A1) fails to show wherein the bonding pad extends over and in direct contact with the second porous dielectric portion before the heat treatment process is performed, and the bonding pad is separated from the second porous dielectric portion by a second air gap after the heat treatment process is performed. These features in combination with other elements in the claim are neither disclosed nor suggested by the prior art of record.
Regarding claim 6, the primary art of record, Shih (US 20210287937 A1) fails to show wherein before the bonding pad is formed, the method further comprises: forming a first via hole and a second via hole in the dielectric layer to partially expose the first interconnect portion of the interconnect structure, wherein the first via hole and the second via hole expose opposite sidewalls of the second porous dielectric portion; and filling the first via hole and the second via hole with a first conductive via and a second conductive via, respectively. These features in combination with other elements in the claim are neither disclosed nor suggested by the prior art of record.
Conclusion
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/THOMAS WILSON MCCOY/ Examiner, Art Unit 2814 /WAEL M FAHMY/Supervisory Patent Examiner, Art Unit 2814
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