DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claims 3 and 7 are objected to because of the following informalities: in line 3 of each claim, replace “more ofen” with --more often--. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 8 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 8 recites the limitation "the non-transitory computer readable storage medium of claim 1" in line 1. There is insufficient antecedent basis for this limitation in the claim. It is believed the claim should instead recite --the non-transitory computer readable storage medium of claim 5--.
Appropriate correction is therefore required.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Applicant is advised that this Double Patenting rejection will not be held in abeyance. See MPEP § 804(I)(B)(1); 37 CFR § 1.111(b).
Claims 1-8 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1 and 8 of U.S. Patent No. 12,306,689 in view of Roy et al. (U.S. Patent Application Publication Number 2019/0339757) and Weekly (U.S. Patent Application Publication Number 2009/0063065). The conflicting patent claims do not require stagger when at least some of the compute units start to perform the respective operations on the data to mitigate the supply voltage droop (Claims 1 and 5) and wherein the stagger is applied to different groups of the compute units concurrently (Claims 4 and 8). However, Roy teaches these features (Roy, paragraphs 0019, 0024, and 0030). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have combined Roy’s teachings of voltage droop mitigation techniques with the teachings of the conflicting patent claims, for the purpose of preventing voltage droop, thereby reducing various function errors in the circuits (see Roy, paragraph 0019).
The conflicting patent claims also do not require wherein the configuration information is further provided for use by the integrated circuit to detect inactivity for a predetermined number of clock cycles by each of the compute units, wherein the staggering when at least some of the compute units start to perform the respective operations is based both on an initial start of execution of the dataflow graph by the integrated circuit and on the inactivity detected subsequent to the initial start of execution of the dataflow graph (Claims 2 and 6) and wherein the configuration information prioritizes the start of performance of a type of operation that tends to experience the inactivity more often than other types of operations (Claims 3 and 7). However, Weekly teaches these features (Weekly, paragraphs 0044-0045). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have combined Weekly’s teachings of voltage droop mitigation techniques with the teachings of the conflicting patent claims, for the purpose of avoiding the need to modify the voltage guard band. Instead, the combination would allow a more optimal scheduling of operations such that all of the operations can be executed within the voltage supply margins.
Instant Claims
Claims of U.S. Patent 12,306,689
1. A method comprising:
analyzing a dataflow graph to generate configuration information loadable into an integrated circuit, wherein the dataflow graph specifies operations to be performed and data dependencies between the operations; and
providing the configuration information for use by the integrated circuit to:
configure compute units of the integrated circuit to perform respective one or more of the operations of the dataflow graph;
control data flow between the compute units to accomplish the data dependencies between the respective operations performed by the compute units;
control when each compute unit starts to perform the respective operations on the data to mitigate supply voltage droop caused by a time rate of change of current drawn by the integrated circuit through inductive loads of the integrated circuit;
guarantee that, during execution of the dataflow graph, no more than a predetermined number of compute units concurrently start to perform the respective operations; and
stagger when at least some of the compute units start to perform the respective operations on the data to mitigate the supply voltage droop.
1. A method, comprising: analyzing a dataflow graph to generate configuration information loadable into an integrated circuit, wherein the dataflow graph specifies operations to be performed and data dependencies between the operations; providing the configuration information for use by the integrated circuit to: configure compute units of the integrated circuit to perform respective one or more of the operations of the dataflow graph; control data flow between the compute units to accomplish the data dependencies between the respective operations performed by the compute units; control when each compute unit starts to perform the respective operations on the data to mitigate supply voltage droop caused by a time rate of change of current drawn by the integrated circuit through inductive loads of the integrated circuit; and guarantee that a delay of at least a predetermined number of clock cycles intervenes between each instance in which no more than the predetermined number of the compute units concurrently start to perform the respective operations.
+
Roy, paragraphs 0019 and 0024 (staggering feature)
2. The method of claim 1, wherein the configuration information is further provided for use by the integrated circuit to:
detect inactivity for a predetermined number of clock cycles by each of the compute units,
wherein the staggering when at least some of the compute units start to perform the respective operations is based both on an initial start of execution of the dataflow graph by the integrated circuit and on the inactivity detected subsequent to the initial start of execution of the dataflow graph.
Weekly, paragraphs 0044-0045; i.e., the processor activity is found to be from nearly no executions [i.e., “inactivity for a predetermined number of clock cycles”] to being active for 90% of the subsequent cycles; the decision to stall/stagger the execution of each execution unit 104 is based on both the inactivity as well as the ordering of the particular computer program
3. The method of claim 2, wherein the configuration information prioritizes the start of performance of a type of operation that tends to experience the inactivity more often than other types of operations.
Weekly, paragraph 0044; i.e., an execution unit 104 that has nearly no executions for a time period [“tends to experience inactivity”] is given priority in that none of its execution requests are stalled thereafter
4. The method of claim 1, wherein the stagger is applied to different groups of the compute units concurrently.
Roy, paragraphs 0024 and 0030; i.e., the staggering of the wake up signals can occur at different clock domains [“different groups”]
5. A non-transitory computer-readable storage medium storing computer program instructions, wherein the computer program instructions, when executed on a processor, implement a method comprising:
analyzing a dataflow graph to generate configuration information loadable into an integrated circuit, wherein the dataflow graph specifies operations to be performed and data dependencies between the operations;
wherein the configuration information is usable by the integrated circuit to:
configure compute units of the integrated circuit to perform respective one or more of the operations of the dataflow graph;
control data flow between the compute units to accomplish the data dependencies between the respective operations performed by the compute units;
control when each compute unit starts to perform the respective operations on the data to mitigate supply voltage droop caused by a time rate of change of current drawn by the integrated circuit through inductive loads of the integrated circuit;
guarantee that a delay of at least a predetermined number of clock cycles intervenes between each instance in which no more than the predetermined number of the compute units concurrently start to perform the respective operations; and
stagger when at least some of the compute units start to perform the respective operations on the data to mitigate the supply voltage droop.
8. A non-transitory computer-readable storage medium storing computer program instructions, wherein the computer program instructions, when executed on a processor, implement a method comprising: analyzing a dataflow graph to generate configuration information loadable into an integrated circuit, wherein the dataflow graph specifies operations to be performed and data dependencies between the operations; wherein the configuration information is usable by the integrated circuit to: configure compute units of the integrated circuit to perform respective one or more of the operations of the dataflow graph; control data flow between the compute units to accomplish the data dependencies between the respective operations performed by the compute units; control when each compute unit starts to perform the respective operations on the data to mitigate supply voltage droop caused by a time rate of change of current drawn by the integrated circuit through inductive loads of the integrated circuit; and guarantee that a delay of at least a predetermined number of clock cycles intervenes between each instance in which no more than the predetermined number of the compute units concurrently start to perform the respective operations.
+
Roy, paragraphs 0019 and 0024 (staggering feature)
6. The non-transitory computer readable storage medium of claim 5, wherein the configuration information is further usable by the integrated circuit to: detect inactivity for a predetermined number of clock cycles by each of the compute units, wherein the staggering when at least some of the compute units start to perform the respective operations is based both on an initial start of execution of the dataflow graph by the integrated circuit and on the inactivity detected subsequent to the initial start of execution of the dataflow graph.
Weekly, paragraphs 0044-0045; i.e., the processor activity is found to be from nearly no executions [i.e., “inactivity for a predetermined number of clock cycles”] to being active for 90% of the subsequent cycles; the decision to stall/stagger the execution of each execution unit 104 is based on both the inactivity as well as the ordering of the particular computer program
7. The non-transitory computer readable storage medium of claim 6, wherein the configuration information prioritizes the start of performance of a type of operation that tends to experience the inactivity more often than other types of operations.
Weekly, paragraph 0044; i.e., an execution unit 104 that has nearly no executions for a time period [“tends to experience inactivity”] is given priority in that none of its execution requests are stalled thereafter
8. The non-transitory computer readable storage medium of claim 1, wherein the stagger is applied to different groups of the compute units concurrently.
Roy, paragraphs 0024 and 0030; i.e., the staggering of the wake up signals can occur at different clock domains [“different groups”]
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-8 are rejected under 35 U.S.C. 103 as being unpatentable over Keceli et al. (U.S. Patent Application Publication Number 2019/0041942), Weekly (U.S. Patent Application Publication Number 2009/0063065), and Roy et al. (U.S. Patent Application Publication Number 2019/0339757).
Regarding Claims 1 and 5, Keceli discloses a method (and a non-transitory computer-readable storage medium storing computer program instructions, wherein the computer program instructions, when executed on a processor [Figure 1, item 106], implement a method [as required by Claim 5]) (paragraph 0041) comprising:
analyzing (Figure 1, item 114, paragraph 0023) a dataflow graph (paragraph 0018) to generate configuration information loadable into an integrated circuit (Figure 1, item 100, paragraph 0010; i.e., a system on a chip), wherein the dataflow graph specifies operations to be performed and data dependencies between the operations (paragraph 0023); and
providing the configuration information for use by the integrated circuit to:
configure compute units (Figure 1, item 106, paragraph 0011) of the integrated circuit to perform respective one or more of the operations (paragraph 0013) of the dataflow graph (paragraph 0019);
control data flow between the compute units to accomplish the data dependencies between the respective operations performed by the compute units (paragraphs 0020-0021).
Keceli does not expressly disclose control when each compute unit starts to perform the respective operations on the data to mitigate supply voltage droop caused by a time rate of change of current drawn by the integrated circuit through inductive loads of the integrated circuit;
guarantee that, during execution of the dataflow graph, no more than a predetermined number of compute units concurrently start to perform the respective operations; and
stagger when at least some of the compute units start to perform the respective operations on the data to mitigate the supply voltage droop.
In the same field of endeavor (e.g., voltage droop mitigation techniques), Weekly teaches controlling when each compute unit (Figure 1, item 104, paragraph 0046; i.e., there may be plural execution units 104) starts to perform the respective operations on the data to mitigate supply voltage droop caused by a time rate of change of current (Figure 10A, item 1002, paragraphs 0058-0059; i.e., step current changes) drawn by the integrated circuit through inductive loads (paragraph 0005; i.e., as explained in the instant specification [paragraphs 0004-0005], voltage droop in integrated circuits is caused by a large rate of change of current drawn through inductive loads) of the integrated circuit (paragraph 0036; i.e., the voltage monitor/throttle request determiner 106 can stall [i.e., control when it starts] each execution unit 104 from performing a task if the task would result in voltage droop occurring); and
guarantee that, during execution of the dataflow graph (paragraph 0035; i.e., there may be a plurality of tasks for the execution units 104 to perform; as discussed above, Keceli discloses executing tasks in the form of a dataflow graph), no more than a predetermined number of the compute units concurrently start to perform the respective operations (paragraph 0036; i.e., certain of the compute units 104 may be stalled if their execution would result in unacceptable voltage droop - therefore it is "guaranteed" that the specific number of execution units 104 that are allowed to operate [the "predetermined number"] are concurrently able to start to perform their respective operations).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have combined Weekly’s teachings of voltage droop mitigation techniques with the teachings of Keceli, for the purpose of avoiding the need to modify the voltage guard band. Instead, the combination would allow a more optimal scheduling of operations such that all of the operations can be executed within the voltage supply margins.
Also in the same field of endeavor (e.g., voltage droop mitigation techniques), Roy teaches stagger when at least some of the compute units (Figure 1, items 130, paragraph 0023) start to perform the respective operations on the data to mitigate the supply voltage droop (paragraphs 0019 and 0024).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have combined Roy’s teachings of voltage droop mitigation techniques with the teachings of Keceli, for the purpose of preventing voltage droop, thereby reducing various function errors in the circuits (see Roy, paragraph 0019).
Regarding Claims 2 and 6, Weekly teaches wherein the configuration information is further provided for use by the integrated circuit to detect inactivity for a predetermined number of clock cycles by each of the compute units, wherein the staggering when at least some of the compute units start to perform the respective operations is based both on an initial start of execution of the dataflow graph by the integrated circuit and on the inactivity detected subsequent to the initial start of execution of the dataflow graph (paragraphs 0044-0045; i.e., the processor activity is found to be from nearly no executions [i.e., “inactivity for a predetermined number of clock cycles”] to being active for 90% of the subsequent cycles; the decision to stall/stagger the execution of each execution unit 104 is based on both the inactivity as well as the ordering of the particular computer program).
Regarding Claims 3 and 7, Weekly teaches wherein the configuration information prioritizes the start of performance of a type of operation that tends to experience the inactivity more often than other types of operations (paragraph 0044; i.e., an execution unit 104 that has nearly no executions for a time period [“tends to experience inactivity”] is given priority in that none of its execution requests are stalled thereafter).
Regarding Claims 4 and 8, Roy teaches wherein the stagger is applied to different groups of the compute units concurrently (paragraphs 0024 and 0030; i.e., the staggering of the wake up signals can occur at different clock domains [“different groups”]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure because each reference discloses methods for mitigating voltage droop.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FAISAL M ZAMAN whose telephone number is (571)272-6495. The examiner can normally be reached Monday - Friday, 8 am - 5 pm, alternate Fridays.
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/FAISAL M ZAMAN/ Primary Examiner, Art Unit 2175
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