DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Applicant is advised that this Double Patenting rejection will not be held in abeyance. See MPEP § 804(I)(B)(1); 37 CFR § 1.111(b).
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-5 and 7-20 of U.S. Patent No. 12,332,837 in view of Moita et al. (U.S. Patent Application Publication Number 2021/0004263). The conflicting patent claims do not expressly require selecting a currently inserted node from an ordered data structure; and inserting the currently inserted node at the end of the ordered sequence of nodes (see Claims 1, 15, and 20; lines 7-9, 9-11, and 8-10, respectively). However, Moita teaches these features. More specifically, Moita teaches selecting a currently inserted node from an ordered data structure (Figure 2A, item 204, paragraph 0022; i.e., the parent nodes 0, 1, and 9 are selected from the “ordered data structure” S). Moita further teaches inserting the currently inserted node at the end of the ordered sequence of nodes (Figure 2B, item 202, paragraphs 0023 and 0025; i.e., the “currently inserted nodes” 0, 1, and 9 are inserted into the tail/end of the “ordered sequence of nodes” L). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have combined Moita’s teachings of sorting nodes of an operation unit graph with the teachings of the conflicting patent, for the purpose of reducing resource conflicts with a resource used by a previous node, resolving larger numbers of dependencies early, and forcing early resolution of resource conflicts (see Moita, abstract) and further for improving task sorting without requiring expensive optimization computations (see Moita, paragraph 0002).
Instant Claims
Claims of U.S. Patent 12,332,837
1. A method of operating a compiler that is executable in one or more processors coupled to a storage medium comprising:
receiving an operation unit graph comprising a set of unsorted nodes and edges that interconnect nodes in the set of unsorted nodes;
determining an ordered sequence of nodes from the set of unsorted nodes, comprising:
selecting a currently inserted node from an ordered data structure;
inserting the currently inserted node at the end of the ordered sequence of nodes; and
adding neighboring nodes of the currently inserted node from the set of unsorted nodes that are separated from the currently inserted node by one of the edges to the ordered data structure;
receiving a hardware description describing a reconfigurable processor; and
using the hardware description to determine an assignment of the nodes of the ordered sequence of nodes in order of the ordered sequence of nodes onto the reconfigurable processor during placement of the operation unit graph.
1. A method of operating a compiler that is executable in one or more processors coupled to a storage medium comprising: receiving an operation unit graph comprising a set of unsorted nodes and edges that interconnect nodes in the set of unsorted nodes; determining a first position of an ordered sequence of nodes as a current position of the ordered sequence of nodes; repeating as long as the set of unsorted nodes comprises at least one unsorted node: determining, from the set of unsorted nodes, a node-to-be-sorted in the operation unit graph; adding the node-to-be-sorted to an ordered data structure; and repeating until the ordered data structure is empty: in order of the ordered data structure, removing a next node-to-be-sorted from the ordered data structure, inserting the next node-to-be-sorted as the currently inserted node at the current position of the ordered sequence of nodes, assigning a subsequent position of the ordered sequence of nodes as the current position of the ordered sequence of nodes, determining neighboring nodes of the currently inserted node from the set of unsorted nodes, wherein each one of the neighboring nodes is separated from the currently inserted node by one of the edges, adding each one of the neighboring nodes as a node-to-be-sorted to the ordered data structure, and removing the currently inserted node from the set of unsorted nodes; receiving a hardware description describing a reconfigurable processor having interconnects, physical compute units and/or physical memory units; using the hardware description to determine an assignment of the edges and nodes of the ordered sequence of nodes onto the interconnects, the physical compute units and/or the physical memory units of the reconfigurable processor during placement and routing of the operation unit graph; and generating a configuration file that is adapted for being applied to the reconfigurable processor for configuring the reconfigurable processor with the assignment of the edges and the nodes of the ordered sequence of nodes onto the interconnects, the physical compute units and/or the physical memory units. + Moita, paragraphs 0022, 0023, and 0025
2. The method of claim 1, wherein determining an ordered sequence of nodes from the set of unsorted nodes further comprises:
determining a set of input nodes in the set of unsorted nodes, wherein input nodes in the set of input nodes exclusively transmit data over the edges to other nodes in the set of unsorted nodes; and
determining a set of output nodes in the set of unsorted nodes, wherein output nodes in the set of output nodes exclusively receive data over the edges from other nodes in the set of unsorted nodes.
2. The method of claim 1, wherein determining, from the set of unsorted nodes, the node-to-be-sorted in the operation unit graph further comprises: determining a set of input nodes in the set of unsorted nodes, wherein input nodes in the set of input nodes exclusively transmit data over the edges to other nodes in the set of unsorted nodes; and determining a set of output nodes in the set of unsorted nodes, wherein output nodes in the set of output nodes exclusively receive data over the edges from other nodes in the set of unsorted nodes.
3.The method of claim 2, further comprising:
determining a longest path in the operation unit graph, wherein the longest path starts from a first node in the set of input nodes and ends at a second node in the set of output nodes; and
inserting the first node or the second node at a first position of the ordered data structure.
3. The method of claim 2, wherein determining, from the set of unsorted nodes, the node-to-be-sorted in the operation unit graph further comprises: determining a longest path in the operation unit graph, wherein the longest path starts from a first node in the set of input nodes and ends at a second node in the set of output nodes; and selecting the first node or the second node as the node-to-be-sorted.
4. The method of claim 2, further comprising:
determining a provisioned bandwidth for each edge of the edges that is connected to an input node of the input nodes; and
inserting at a first position of the ordered data structure the input node among the input nodes that is connected to the edge of the edges with a greatest provisioned bandwidth.
4. The method of claim 2, wherein determining, from the set of unsorted nodes, the node-to-be-sorted in the operation unit graph further comprises: determining a provisioned bandwidth for each edge of the edges that is connected to an input node of the input nodes; and selecting as the node-to-be-sorted the input node among the input nodes that is connected to the edge of the edges with a greatest provisioned bandwidth. + Moita, paragraph 0023
5. The method of claim 2, further comprising:
determining a provisioned bandwidth for each edge of the edges that is connected to an output node in the set of output nodes; and
inserting at a first position of the ordered data structure the output node among the output nodes that is connected to the edge of the edges with a greatest provisioned bandwidth.
5. The method of claim 2, wherein determining, from the set of unsorted nodes, the node-to-be-sorted in the operation unit graph further comprises: determining a provisioned bandwidth for each edge of the edges that is connected to an output node in the set of output nodes; and selecting as the node-to-be-sorted the output node among the output nodes that is connected to the edge of the edges with a greatest provisioned bandwidth. + Moita, paragraph 0023
6. The method of claim 1, further comprising:
removing the currently inserted node from the ordered data structure and from the set of unsorted nodes.
1. A method of operating a compiler that is executable in one or more processors coupled to a storage medium comprising: receiving an operation unit graph comprising a set of unsorted nodes and edges that interconnect nodes in the set of unsorted nodes; determining a first position of an ordered sequence of nodes as a current position of the ordered sequence of nodes; repeating as long as the set of unsorted nodes comprises at least one unsorted node: determining, from the set of unsorted nodes, a node-to-be-sorted in the operation unit graph; adding the node-to-be-sorted to an ordered data structure; and repeating until the ordered data structure is empty: in order of the ordered data structure, removing a next node-to-be-sorted from the ordered data structure, inserting the next node-to-be-sorted as the currently inserted node at the current position of the ordered sequence of nodes, assigning a subsequent position of the ordered sequence of nodes as the current position of the ordered sequence of nodes, determining neighboring nodes of the currently inserted node from the set of unsorted nodes, wherein each one of the neighboring nodes is separated from the currently inserted node by one of the edges, adding each one of the neighboring nodes as a node-to-be-sorted to the ordered data structure, and removing the currently inserted node from the set of unsorted nodes; receiving a hardware description describing a reconfigurable processor having interconnects, physical compute units and/or physical memory units; using the hardware description to determine an assignment of the edges and nodes of the ordered sequence of nodes onto the interconnects, the physical compute units and/or the physical memory units of the reconfigurable processor during placement and routing of the operation unit graph; and generating a configuration file that is adapted for being applied to the reconfigurable processor for configuring the reconfigurable processor with the assignment of the edges and the nodes of the ordered sequence of nodes onto the interconnects, the physical compute units and/or the physical memory units.
7. The method of claim 6, wherein adding the neighboring nodes to the ordered data structure further comprises:
determining a ranking of nodes-to-be-ranked, wherein the nodes-to-be-ranked comprise the neighboring nodes and each node in the ordered data structure;
rearranging each node in the ordered data structure according to the ranking; and
inserting each one of the neighboring nodes according to the ranking into the ordered data structure.
7. The method of claim 1, wherein adding each one of the neighboring nodes as a node-to-be-sorted to the ordered data structure further comprises: determining a ranking of nodes-to-be-ranked, wherein the nodes-to-be-ranked comprise the neighboring nodes and each node-to-be-sorted in the ordered data structure; rearranging each node-to-be-sorted in the ordered data structure according to the ranking; and inserting each one of the neighboring nodes as a node-to-be-sorted according to the ranking into the ordered data structure.
8. The method of claim 7, wherein determining the ranking of the nodes-to-be-ranked further comprises:
determining a series of keys for each one of the nodes-to-be-ranked, wherein the ranking of the nodes-to-be-ranked is based on the series of keys.
8. The method of claim 7, wherein determining the ranking of the nodes-to-be-ranked further comprises: determining a series of keys for each one of the nodes-to-be-ranked, wherein the ranking of the nodes-to-be-ranked is based on the series of keys.
9. The method of claim 8, wherein determining the ranking of the nodes-to-be-ranked further comprises:
determining the ranking of the nodes-to-be-ranked based on a first key in the series of keys.
9. The method of claim 8, wherein determining the ranking of the nodes-to-be-ranked further comprises: determining the ranking of the nodes-to-be-ranked based on a first key in the series of keys.
10. The method of claim 9, wherein determining the ranking of the nodes-to-be-ranked further comprises:
determining whether nodes of the nodes-to-be-ranked have the same first key; and
in response to determining that nodes of the nodes-to-be-ranked have the same first key, ranking the nodes of the nodes-to-be-ranked with the same first key among themselves based on subsequent keys in the series of keys.
10. The method of claim 9, wherein determining the ranking of the nodes-to-be-ranked further comprises: determining whether nodes of the nodes-to-be-ranked have the same first key; and in response to determining that nodes of the nodes-to-be-ranked have the same first key, ranking the nodes of the nodes-to-be-ranked with the same first key among themselves based on subsequent keys in the series of keys.
11. The method of claim 8, wherein determining the series of keys for each one of the nodes-to-be-ranked further comprises:
determining a key of the series of keys for a current node of the nodes-to-be-ranked based on a cost function of the current node of the nodes-to-be-ranked.
11. The method of claim 8, wherein determining the series of keys for each one of the nodes-to-be-ranked further comprises: determining a key of the series of keys for a current node of the nodes-to-be-ranked based on a cost function of the current node of the nodes-to-be-ranked.
12. The method of claim 11, wherein the cost function of the current node is determined based on at least one criterion.
12. The method of claim 11, wherein the cost function of the current node is determined based on at least one criterion.
13. The method of claim 12, wherein the cost function of the current node is based on a weighted sum of the at least one criterion and at least one additional criterion.
13. The method of claim 12, wherein the cost function of the current node is based on a weighted sum of the at least one criterion and at least one additional criterion.
14. The method of claim 12, wherein a criterion of the at least one criterion comprises at least one of
a number of nodes in the ordered sequence of nodes that is connected to the current node,
a maximum bandwidth of all edges connected to the current node,
a maximum bandwidth of any edge connected to the current node and another node in the ordered sequence of nodes,
a minimum bandwidth of all edges connected to the current node,
a minimum bandwidth of any edge connected to the current node and another node in the ordered sequence of nodes,
a maximum fanout of the current node,
a number of edges that are connected to the current node and part of a virtual channel, or
a number of iterations that the current node has been in the ordered data structure while the next node-to-be-sorted has been removed from the ordered data structure.
14. The method of claim 12, wherein a criterion of the at least one criterion comprises at least one of a number of nodes in the ordered sequence of nodes that is connected to the current node, a maximum bandwidth of all edges connected to the current node, a maximum bandwidth of any edge connected to the current node and another node in the ordered sequence of nodes, a minimum bandwidth of all edges connected to the current node, a minimum bandwidth of any edge connected to the current node and another node in the ordered sequence of nodes, a maximum fanout of the current node, a number of edges that are connected to the current node and part of a virtual channel, or a number of iterations that the current node has been in the ordered data structure while the next node-to-be-sorted has been removed from the ordered data structure.
15. A system, comprising:
one or more host processors coupled to a storage medium; and
a compiler executable in any one of the one or more host processors, wherein the compiler is configured to:
receive an operation unit graph comprising a set of unsorted nodes and edges that interconnect nodes in the set of unsorted nodes;
determine an ordered sequence of nodes from the set of unsorted nodes, comprising:
select a currently inserted node from an ordered data structure;
insert the currently inserted node at the end of the ordered sequence of nodes; and
add neighboring nodes of the currently inserted node from the set of unsorted nodes that are separated from the currently inserted node by one of the edges to the ordered data structure;
receive a hardware description describing a reconfigurable processor; and
use the hardware description to determine an assignment of the nodes of the ordered sequence of nodes in order of the ordered sequence of nodes onto the reconfigurable processor during placement of the operation unit graph.
15. A system, comprising: one or more host processors coupled to a storage medium; and a compiler executable in any one of the one or more host processors, wherein the compiler is configured to: receive an operation unit graph comprising a set of unsorted nodes and edges that interconnect nodes in the set of unsorted nodes; determine a first position of an ordered sequence of nodes as a current position of the ordered sequence of nodes; repeat as long as the set of unsorted nodes comprises at least one unsorted node: determine, from the set of unsorted nodes, a node-to-be-sorted in the operation unit graph; add the node-to-be-sorted to an ordered data structure; and repeat until the ordered data structure is empty: in order of the ordered data structure, remove a next node-to-be-sorted from the ordered data structure, insert the next node-to-be-sorted as the currently inserted node at the current position of the ordered sequence of nodes, assign a subsequent position of the ordered sequence of nodes as the current position of the ordered sequence of nodes, determine neighboring nodes of the currently inserted node from the set of unsorted nodes, wherein each one of the neighboring nodes is separated from the currently inserted node by one of the edges, add each one of the neighboring nodes as a node-to-be-sorted to the ordered data structure, and remove the currently inserted node from the set of unsorted nodes; receive a hardware description describing a reconfigurable processor having interconnects, physical compute units and/or physical memory units; use the hardware description and the ordered sequence of nodes to determine an assignment of the edges and nodes of the ordered sequence of nodes onto the interconnects, the physical compute units and/or the physical memory units during placement and routing of the operation unit graph; and generating a configuration file that is adapted for being applied to the reconfigurable processor for configuring the reconfigurable processor with the assignment of the edges and the nodes of the ordered sequence of nodes onto the interconnects, the physical compute units and/or the physical memory units. + Moita, paragraphs 0022, 0023, and 0025
16. The system of claim 15, wherein the compiler is further configured to:
remove the currently inserted node from the ordered data structure and from the set of unsorted nodes;
determine a ranking of nodes-to-be-ranked, wherein the nodes-to-be-ranked comprise the neighboring nodes and each node-to-be-sorted in the ordered data structure;
rearrange each node-to-be-sorted in the ordered data structure according to the ranking; and
insert the neighboring nodes as a node-to-be-sorted according to the ranking into the ordered data structure.
16. The system of claim 15, wherein the compiler, for adding each one of the neighboring nodes as a node-to-be-sorted to the ordered data structure, is further configured to: determine a ranking of nodes-to-be-ranked, wherein the nodes-to-be-ranked comprise the neighboring nodes and each node-to-be-sorted in the ordered data structure; rearrange each node-to-be-sorted in the ordered data structure according to the ranking; and insert each one of the neighboring nodes as a node-to-be-sorted according to the ranking into the ordered data structure.
17. The system of claim 16, wherein the compiler, for determining the ranking of the nodes-to-be-ranked, is further configured to:
determine a series of keys for each one of the nodes-to-be-ranked, wherein the ranking of the nodes-to-be-ranked is based on the series of keys.
17. The system of claim 16, wherein the compiler, for determining the ranking of the nodes-to-be-ranked, is further configured to: determine a series of keys for each one of the nodes-to-be-ranked, wherein the ranking of the nodes-to-be-ranked is based on the series of keys.
18. The system of claim 17, wherein the compiler, for determining the ranking of the nodes-to-be-ranked, is further configured to:
determine the ranking of the nodes-to-be-ranked based on a first key in the series of keys;
determine whether nodes of the nodes-to-be-ranked have the same first key; and
in response to determining that nodes of the nodes-to-be-ranked have the same first key, rank the nodes of the nodes-to-be-ranked with the same first key among themselves based on subsequent keys in the series of keys.
18. The sorting tool system of claim 17, wherein the compiler, for determining the ranking of the nodes-to-be-ranked, is further configured to: determine the ranking of the nodes-to-be-ranked based on a first key in the series of keys; determine whether nodes of the nodes-to-be-ranked have the same first key; and in response to determining that nodes of the nodes-to-be-ranked have the same first key, rank the nodes of the nodes-to-be-ranked with the same first key among themselves based on subsequent keys in the series of keys.
19. The system of claim 17, wherein the compiler, for determining the series of keys for each one of the nodes-to-be-ranked, is further configured to:
determine a key of the series of keys for a current node of the nodes-to-be-ranked based on a cost function of the current node of the nodes-to-be-ranked.
19. The system of claim 17, wherein the compiler, for determining the series of keys for each one of the nodes-to-be-ranked, is further configured to: determine a key of the series of keys for a current node of the nodes-to-be-ranked based on a cost function of the current node of the nodes-to-be-ranked.
20. A non-transitory computer-readable storage medium including instructions that, when executed by a processing unit, cause the processing unit to operate a compiler, the instructions comprising:
receiving an operation unit graph comprising a set of unsorted nodes and edges that interconnect nodes in the set of unsorted nodes;
determining an ordered sequence of nodes from the set of unsorted nodes, comprising:
selecting a currently inserted node from an ordered data structure;
inserting the currently inserted node at the end of the ordered sequence of nodes; and
adding neighboring nodes of the currently inserted node from the set of unsorted nodes that are separated from the currently inserted node by one of the edges to the ordered data structure;
receiving a hardware description describing a reconfigurable processor; and
using the hardware description to determine an assignment of the nodes of the ordered sequence of nodes in order of the ordered sequence of nodes onto the reconfigurable processor during placement of the operation unit graph.
20. A non-transitory computer-readable storage medium including instructions that, when executed by a processing unit, cause the processing unit to operate a compiler, the instructions comprising: receiving an operation unit graph comprising a set of unsorted nodes and edges that interconnect nodes in the set of unsorted nodes; determining a first position of an ordered sequence of nodes as a current position of the ordered sequence of nodes; repeating as long as the set of unsorted nodes comprises at least one unsorted node: determining, from the set of unsorted nodes, a node-to-be-sorted in the operation unit graph; adding the node-to-be-sorted to an ordered data structure; and repeating until the ordered data structure is empty: in order of the ordered data structure, removing a next node-to-be-sorted from the ordered data structure, inserting the next node-to-be-sorted as the currently inserted node at the current position of the ordered sequence of nodes, assigning a subsequent position of the ordered sequence of nodes as the current position of the ordered sequence of nodes, determining neighboring nodes of the currently inserted node from the set of unsorted nodes, wherein each one of the neighboring nodes is separated from the currently inserted node by one of the edges, adding each one of the neighboring nodes as a node-to-be-sorted to the ordered data structure, and removing the currently inserted node from the set of unsorted nodes; and receiving a hardware description describing a reconfigurable processor having interconnects, physical compute units and/or physical memory units; using the hardware description to determine an assignment of the edges and nodes of the ordered sequence of nodes onto the interconnects, the physical compute units and/or the physical memory units of the reconfigurable processor during placement and routing of the operation unit graph; and generating a configuration file that is adapted for being applied to the reconfigurable processor for configuring the reconfigurable processor with the assignment of the edges and the nodes of the ordered sequence of nodes onto the interconnects, the physical compute units and/or the physical memory units. + Moita, paragraphs 0022, 0023, and 0025
Allowable Subject Matter
Claims 1-20 would be allowable if the Double Patenting rejection discussed above was overcome.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding Claims 1, 15, and 20, the prior art of record does not teach “receiving a hardware description describing a reconfigurable processor; and using the hardware description to determine an assignment of the nodes of the ordered sequence of nodes in order of the ordered sequence of nodes onto the reconfigurable processor during placement of the operation unit graph” (as recited in Claim 1, and similarly in Claims 15 and 20), in conjunction with the other limitations in each claim.
The closest prior art references of record are Rawat et al. (U.S. Patent Number 10,872,057) and Beyer (U.S. Patent Application Publication Number 2018/0167289).
Rawat discloses sorting a plurality of unsorted nodes in an operation unit graph for placement on a reconfigurable processor. See Rawat, Column 13, lines 57 - Column 14, line 7. The process is repeated until all nodes in the graph are sorted. However, Rawat does not teach receiving a hardware description describing a reconfigurable processor and using the hardware description to determine an assignment of the nodes of the ordered sequence of nodes in order of the ordered sequence of nodes onto the reconfigurable processor during placement of the operation unit graph as required by the claims.
Beyer also discloses sorting a plurality of unsorted nodes for a reconfigurable processor. See Beyer, paragraphs 0041-0042. The sorting is based on a weighting process. However, Beyer does not teach receiving a hardware description describing a reconfigurable processor and using the hardware description to determine an assignment of the nodes of the ordered sequence of nodes in order of the ordered sequence of nodes onto the reconfigurable processor during placement of the operation unit graph as required by the claims.
All claims that are not specifically addressed are allowable due to a dependency.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure because each reference discloses methods for sorting nodes of an operation unit graph and further using that sorting for a compiler.
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/FAISAL M ZAMAN/ Primary Examiner, Art Unit 2175
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