Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This action is in response to the preliminary amendment 04/12/2026.
Claims 1 and 3 are cancelled.
Claims 4 – 28 are new.
Claims 2 and 4 – 28 are presented for examination.
Priority
Applicant’s claim for the benefit of a prior-filed application under 35 U.S.C. 120 is acknowledged.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the claims at issue are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the reference application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
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Claims XX are rejected on the ground of nonstatutory double patenting over claims XX of U.S. Patent No. 12,282,064 since the claims, if allowed, would improperly extend the “right to exclude” already granted in the patent.
The subject matter claimed in the instant application is fully disclosed in the patent and is covered by the patent since the patent and the application are claiming common subject matter, as follows:
Claim 2 – Application 19/097656
Claim 1 – Patent 12,282,064
An apparatus, comprising:
An apparatus, comprising:
a component die, comprising:
a component die, comprising:
component circuitry for performing a component function;
component circuitry for performing a component function;
interface circuitry for communicating with a compute die not containing the component circuitry for performing the component function and that controls the component die, the interface circuitry comprising a transmit chain for sending data to the compute die, the transmit chain comprising a packetizer and transmit circuit that creates packets appended with cyclic redundancy check (CRC) values; and
interface circuitry for communicating with a compute die not containing the component circuitry for performing the component function and that controls the component die, the interface circuitry comprising a transmit chain for sending data to the compute die, the transmit chain comprising a packetizer and transmit circuit that creates packets appended with cyclic redundancy check (CRC) values; and
a validation built-in self-test (VBIST) circuit, comprising: a traffic generator that generates test data streams;
a validation built-in self-test (VBIST) circuit, comprising: a traffic generator that generates test data streams;
a tracker that receives and validates test data streams; and
a tracker that receives and validates test data streams; and
a configurable switching matrix capable of providing a first path for data to go from the component circuitry to the tracker without going through the interface circuitry and a second path for data to go from the tracker to the component circuitry without going through the interface circuitry.
a configurable switching matrix capable of:
providing a path for data to go from the traffic generator to the interface circuitry without going through the component circuitry or the tracker,
providing a path for data to go from the traffic generator to the tracker without going through the component circuitry or the interface circuitry,
providing a path for data to go from the component circuitry to the tracker without going through the interface circuitry, and
providing a path for data to go from the interface circuitry to the tracker without going through the component circuitry, according to a mode of operation of the VBIST.
One of ordinary skill in the art would clearly recognize independent claim 2, of application 19/097656 is an obvious variation of the claimed subject matter of independent claim 1, of patent 12,282,064. Specifically, both claim 2, of the current application 19/097656, and claim 1, of patent 12,282,064 discloses: an apparatus, comprising “a component die”, “component circuitry”, “interface circuitry”, “a validation built-in self-test circuit”, “a traffic generator that generates test data streams”, “a tracker that receives and validates test data streams”, and “a configurable switching matrix”.
One of ordinary skill in the art would recognize the apparatus disclosed by claim 2, of the current application 19/097656, as a broad recitation of the operations performed by the apparatus disclosed in claim 1 of Patent 12,282,064. An apparatus performing operations and an apparatus capable of performing the disclosed operations would be recognize by one of ordinary skill in the art as obvious variants of each other.
Therefore, one of ordinary skill in the art would recognize the apparatus claim 2, of the current application 19/097656, as performing the operations of the apparatus of claim 1, of U.S. Patent 12,282,064, and as such are obvious variants of each other.
Claim 4 – Application 19/097656
Claim 1 – Patent 12,282,064
Claim 5 – Application 19/097656
Claim 1 – Patent 12,282,064
Claim 6 – Application 19/097656
Claim 1 – Patent 12,282,064
Claim 7 – Application 19/097656
Claim 1 – Patent 12,282,064
Claim 8 – Application 19/097656
Claim 2 – Patent 12,282,064
Claim 9 – Application 19/097656
Claim 3 – Patent 12,282,064
Claim 10 – Application 19/097656
Claim 4 – Patent 12,282,064
Claim 11 – Application 19/097656
Claim 5 – Patent 12,282,064
Claim 12 – Application 19/097656
Claim 6 – Patent 12,282,064
Claim 13 – Application 19/097656
Claim 7 – Patent 12,282,064
Claim 14 – Application 19/097656
Claim 8 – Patent 12,282,064
Claim 15 – Application 19/097656
Claim 9 – Patent 12,282,064
Claim 16 – Application 19/097656
Claim 10 – Patent 12,282,064
Claim 17 – Application 19/097656
Claim 11 – Patent 12,282,064
Claim 18 – Application 19/097656
Claim 12 – Patent 12,282,064
Claim 19 – Application 19/097656
Claim 13 – Patent 12,282,064
Claim 20 – Application 19/097656
Claim 14 – Patent 12,282,064
Claim 21 – Application 19/097656
Claim 15 – Patent 12,282,064
Claim 22 – Application 19/097656
Claim 16 – Patent 12,282,064
Claim 23 – Application 19/097656
Claim 17 – Patent 12,282,064
Claim 24 – Application 19/097656
Claim 18 – Patent 12,282,064
Claim 25 – Application 19/097656
Claim 19 – Patent 12,282,064
Claim 26 – Application 19/097656
Claim 20 – Patent 12,282,064
Claim 27 – Application 19/097656
Claim 21 – Patent 12,282,064
Claim 28 – Application 19/097656
Claim 22 – Patent 12,282,064
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
KHAN; Raheel et al. US 20170222685 A1
Ferry; Joshua Mason US 20140207402 A1
Bansal; Akash et al. US 20060107154 A1
Volpe; Thomas A. US 10666775 B1
Volpe; Thomas A. US 11076025 B1
Kreider; Thom US 20160370427 A1
Camarota; Rafael C. US 20150008954 A1
Botea; Dragos F. US 20160093400 A1
Alzheimer; Joshua E. et al. US 20230072895 A1
David; Thomas Saroshan et al. US 20230305737 A1
interface circuitry for communicating with a compute die not containing the component circuitry for performing the component function and that controls the component die, the interface circuitry comprising a transmit chain for sending data to the compute die, the transmit chain comprising a packetizer and transmit circuit that creates packets appended with cyclic redundancy check (CRC) values; and
a validation built-in self-test (VBIST) circuit, comprising: a traffic generator that generates test data streams;
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/Daniel F. McMahon/Primary Examiner, Art Unit 2111
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