DETAILED ACTION
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This action is responsive to the following communications: the Application filed February 12, 2025.
Claims 1-9 are pending. Claims 1-5 are amended by preliminary amendments. Claims 6-9 are new. Claims 1 and 5-6 are independent.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55 received on November 19, 2025.
Information Disclosure Statement
Acknowledgment is made of applicant’s Information Disclosure Statement (IDS) filed on May 12, 2025. This IDS has been considered.
Specification
The disclosure is objected to because of the following informalities:
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. See MPEP 606.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-9 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ishizu et al. (U.S. 2021/0265504; hereinafter “Ishizu”).
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Regarding independent claim 1, Ishizu discloses a semiconductor device (Fig. 1) comprising a memory cell (Fig. 5F) comprising:
a first transistor (Fig. 5F: M13) and a second transistor (Fig. 5F: M14),
wherein the first transistor comprises a gate electrode (Fig. 5F: M13 comprises a gate electrode),
wherein the second transistor comprises a gate electrode and a back gate electrode (Fig. 5F: M14 comprises a gate electrode and a back gate electrode),
wherein the gate electrode of the first transistor is electrically connected to a write word line supplying a write word signal (Fig. 5F: gate electrode of M13 is electrically connected to wwl),
wherein one of a source and a drain of the first transistor is electrically connected to a write bit line writing a potential corresponding to data (Fig. 5F: source/drain of M13 is electrically connected to wbl),
wherein the other of the source and the drain of the first transistor is electrically connected to the gate electrode of the second transistor (Fig. 5F: source/drain of M13 is electrically connected to the gate electrode of M14 at node N14),
wherein the back gate electrode of the second transistor is electrically connected to a control signal line supplying a control signal controlling a threshold voltage of the second transistor (Fig. 5F: back gate electrode of M14 is electrically connected to rwlb),
wherein one of a source and a drain of the second transistor is electrically connected to a read word line supplying a read word signal (Fig. 5F: source/drain of M14 is electrically connected to rwl),
wherein the other of the source and the drain of the second transistor is electrically connected to a read bit line reading the potential corresponding to the data (Fig. 5F: source/drain of M14 is electrically connected to rbl),
wherein in the memory cell in a first data reading period when the memory cell is selected, a low level is supplied as the read word signal (during first data reading period, rwl is Vss, see Examiner’s Markup Ishizu’s Figure 7) and a high level is supplied as the control signal (during first data reading period, rwlb is Vdh, see Examiner’s Markup Ishizu’s Figure 7), and
wherein in the memory cell in a second data reading period when the memory cell is not selected, a high level is supplied as the read word signal (during second data reading period, rwl is Vdd, see Examiner’s Markup Ishizu’s Figure 7) and a low level is supplied as the control signal (during second data reading period, rwlb is Vss, see Examiner’s Markup Ishizu’s Figure 7).
Regarding claim 2, Ishizu discloses wherein each of the first transistor and the second transistor is an n-channel transistor (see pages 2-3, par. 0027-0028).
Regarding claim 3, Ishizu discloses wherein each of the first transistor and the second transistor comprises a semiconductor layer comprising a channel formation region (see pages 2-3, par. 0027-0028), and
wherein the semiconductor layer comprises an oxide semiconductor (see page 4, par. 0070-0071).
Regarding claim 4, Ishizu discloses wherein the oxide semiconductor comprises In, Ga, and Zn (see page 5, par. 0082).
Regarding independent claim 5, Ishizu discloses a method for driving a semiconductor device (Fig. 1) comprising a memory cell array (Fig. 1: 210) comprising a memory cell (Fig. 5F) comprising:
a first transistor (Fig. 5F: M13) in which a gate electrode is electrically connected to a write word line supplying a write word signal (Fig. 5F: gate electrode of M13 is electrically connected to wwl) and one of a source and a drain is electrically connected to a write bit line writing a potential corresponding to data (Fig. 5F: source/drain of M13 is electrically connected to wbl); and
a second transistor (Fig. 5F: M14) in which a gate electrode is electrically connected to the other of the source and the drain of the first transistor (Fig. 5F: source/drain of M13 is electrically connected to the gate electrode of M14 at node N14), a back gate electrode is electrically connected to a control signal line supplying a control signal controlling a threshold voltage of the second transistor (Fig. 5F: back gate electrode of M14 is electrically connected to rwlb), one of a source and a drain is electrically connected to a read word line supplying a read word signal (Fig. 5F: source/drain of M14 is electrically connected to rwl), and the other of the source and the drain is electrically connected to a read bit line reading the potential corresponding to the data (Fig. 5F: source/drain of M14 is electrically connected to rbl),
the method comprising:
setting the read word signal to a low level (during first data reading period, rwl is Vss, see Examiner’s Markup Ishizu’s Figure 7) and setting the control signal to a high level in the memory cell in a first data reading period when the memory cell is selected (during first data reading period, rwlb is Vdh, see Examiner’s Markup Ishizu’s Figure 7); and
setting the read word signal to a high level (during second data reading period, rwl is Vdd, see Examiner’s Markup Ishizu’s Figure 7) and setting the control signal to a low level in the memory cell in a second data reading period when the memory cell is not selected (during second data reading period, rwlb is Vss, see Examiner’s Markup Ishizu’s Figure 7).
Regarding independent claim 6, Ishizu discloses a semiconductor device (Fig. 1) comprising a memory cell (Fig. 5F) comprising:
a first transistor (Fig. 5F: M13) and a second transistor (Fig. 5F: M14),
wherein the first transistor comprises a gate electrode (Fig. 5F: M13 comprises a gate electrode),
wherein the second transistor comprises a gate electrode and a back gate electrode (Fig. 5F: M14 comprises a gate electrode and a back gate electrode),
wherein the gate electrode of the first transistor is electrically connected to a first wiring (Fig. 5F: gate electrode of M13 is electrically connected to wwl),
wherein one of a source and a drain of the first transistor is electrically connected to a second wiring writing a potential corresponding to data (Fig. 5F: source/drain of M13 is electrically connected to wbl),
wherein the other of the source and the drain of the first transistor is electrically connected to the gate electrode of the second transistor (Fig. 5F: source/drain of M13 is electrically connected to the gate electrode of M14 at node N14),
wherein the back gate electrode of the second transistor is electrically connected to a third wiring (Fig. 5F: back gate electrode of M14 is electrically connected to rwlb),
wherein one of a source and a drain of the second transistor is electrically connected to a fourth wiring (Fig. 5F: source/drain of M14 is electrically connected to rwl),
wherein the other of the source and the drain of the second transistor is electrically connected to a fifth wiring (Fig. 5F: source/drain of M14 is electrically connected to rbl),
wherein in the memory cell in a first data reading period when the memory cell is selected, a low level is supplied to the fourth wiring (during first data reading period, rwl is Vss, see Examiner’s Markup Ishizu’s Figure 7) and a high level is supplied to the third wiring (during first data reading period, rwlb is Vdh, see Examiner’s Markup Ishizu’s Figure 7), and
wherein in the memory cell in a second data reading period when the memory cell is not selected, a high level is supplied to the fourth wiring (during second data reading period, rwl is Vdd, see Examiner’s Markup Ishizu’s Figure 7) and a low level is supplied to the third wiring (during second data reading period, rwlb is Vss, see Examiner’s Markup Ishizu’s Figure 7).
Regarding claim 7, Ishizu discloses wherein each of the first transistor and the second transistor is an n-channel transistor (see pages 2-3, par. 0027-0028).
Regarding claim 8, Ishizu discloses wherein each of the first transistor and the second transistor comprises a semiconductor layer comprising a channel formation region (see pages 2-3, par. 0027-0028), and
wherein the semiconductor layer comprises an oxide semiconductor (see page 4, par. 0070-0071).
Regarding claim 9, Ishizu discloses wherein the oxide semiconductor comprises In, Ga, and Zn (see page 5, par. 0082).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALFREDO BERMUDEZ LOZADA whose telephone number is (571)272-0877. The examiner can normally be reached 7:00AM-3:30PM EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Alexander G Sofocleous can be reached at 571-272-0635. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Alfredo Bermudez Lozada/ Primary Examiner, Art Unit 2825
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