Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
1. A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on May 18th, 2026 has been entered.
Response to Arguments
2. Applicant’s arguments, filed May 18th, 2026, with respect to the rejections of the independent claims have been fully considered and are persuasive in light of the claim amendments. Therefore, the rejections have been withdrawn. However, upon further consideration, new grounds of rejection are made in view of Wood (US 2002/0116663).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
3. Claims 1-13 are rejected under 35 U.S.C. 103 as being unpatentable over Tu et al (US 2014/0281440, herein Tu) in view of Wood et al (US 2002/0116663, herein Wood).
Regarding claim 1, teaches a processor comprising a logic circuit configured to execute a conditional jump instruction of assembly code under indirect addressing using plural registers including a program counter as a table ([0027-0028], conditional jump using program counter based addressing), the processor being logically configured to execute after storing a jump-destination effective address, storing jump-destination effective addresses that differ from one another in memory space and have a possibility to be specified by a conditional jump instruction, or address offsets from a predetermined reference to jump-destination effective addresses that differ from one another in memory space and have a possibility to be specified by a conditional jump instruction, into plural reference registers respectively, and fetching and decoding a conditional jump instruction that is one instruction that quotes the register ([0047], [0051], [0056], [0068-0070], calculating effective jump address using bits from address registers and instruction);
a first step of acquiring a jump-destination effective address or an address offset from the reference register ([0045-0048], [0051], [0064], acquire address or offset), and;
a second step of setting the acquired jump-destination effective address, or a jump-destination effective address calculated from the acquired address offset, to a register serving as the program counter ([0045-0048], [0064], jump to acquired address).
Tu fails to teach the processor storing a destination address in an index register with an index register number that is generated by using a branch argument associated with a conditional jump instruction, and acquiring the effective address or offset from the index register corresponding to the index register number.
Wood teaches a processor for executing a conditional jump instruction including storing a destination address in an index register with an index register number that is generated by using a branch argument associated with a conditional jump instruction, and acquiring an effective address or address offset from the index register corresponding to the index register number ([0021], indexed jump instructions wherein destination address is based on value of an index register).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the teachings of Tu and Wood to utilize index registers in determining jump destination addresses. While Tu is primarily directed toward the process of correcting a mispredicted destination address of a conditional jump instruction, one of ordinary skill in the art would understand that the use of index registers and jump tables for executing correctly predicted or completed jump instructions is a routine and conventional aspect of the microprocessor art. Therefore, the combination would merely entail a simple substitution of known prior art elements to achieve predictable results, and would have been obvious to one of ordinary skill in the art.
Regarding claim 2, the combination of Tu and Wood teaches the processor as claimed in claim 1, logically configured to execute, after storing, into an index register, an index register number that is an index to a jump-destination effective address, storing jump-destination effective addresses that differ from one another in memory space and have a possibility to be specified by a conditional jump instruction into plural reference registers, respectively, and fetching and decoding a conditional jump instruction that is one instruction that quotes the index register: a first step of acquiring a jump-destination effective address from the reference register corresponding to the index register number that is a content of the index register; and a second step of setting the jump-destination effective address to a register serving as the program counter (Tu [0035], fetch and decode, [0047], [0051], [0056], [0068-0070], calculating effective jump address using bits from address registers and instruction & Wood [0021], indexed jump instructions wherein destination address is based on value of an index register).
Regarding claim 3, the combination of Tu and Wood teaches the processor as claimed in claim 1, logically configured to execute, after storing, into an index register, an index register number that is an index to a jump-destination effective address, storing address offsets from the program counter to jump-destination effective addresses that differ from one another in memory space and have a possibility to be specified by a conditional jump instruction into plural reference registers, respectively, and fetching and decoding a conditional jump instruction that is one instruction that quotes the index register: a first step of acquiring an address offset from the reference register corresponding to the index register number that is a content of the index register; and a second step of setting, to a register serving as the program counter, a jump-destination effective address that is a result of adding the address offset to the program counter (Tu [0035], fetch and decode, [0047], [0051], [0056], [0068-0070], calculating effective jump address using bits from address registers, offsets, and instruction & Wood [0021], indexed jump instructions wherein destination address is based on value of an index register).
Regarding claim 4, the combination of Tu and Wood teaches the processor as claimed in claim 1, logically configured to execute, after storing, into a base resister, a base address in memory space, storing, into an index register, an index register number that is an index to a jump-destination effective address, storing address offsets from the base address to jump-destination effective addresses that differ from one another in memory space and have a possibility to be specified by a conditional jump instruction into plural reference registers, respectively, and fetching and decoding a conditional jump instruction that is one instruction that quotes the index register and the base resister: a first step of acquiring an address offset from the reference register corresponding to the index register number that is a content of the index register; and a second step of setting, to a register serving as the program counter, a jump-destination effective address that is a result of adding the address offset to the base address of the base resister (Tu [0035], fetch and decode, [0047], [0051], [0056], [0068-0070], calculating effective jump address using bits from address registers, offsets, and instruction, base address used to calculate destination address & Wood [0021], indexed jump instructions wherein destination address is based on value of an index register).
Regarding claim 5, the combination of Tu and Wood teaches the processor as claimed in claim 1, wherein the logic circuit is configured by a source code described in a hardware description language or by wired logic (Tu [0076]).
Claims 6-9 refer to a medium embodiment including the limitations present in the processor embodiment of claims 1-4. Therefore, the above rejections for claims 1-4 are applicable to claims 6-9.
Claims 10-13 refer to a method embodiment including the limitations present in the processor embodiment of claims 1-4. Therefore, the above rejections for claims 1-4 are applicable to claims 10-13.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Nakamura (US 2003/0088636) discloses a processor wherein a conditional branch instruction uses a virtual address based on an index register value.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL J METZGER whose telephone number is (571)272-3105. The examiner can normally be reached Monday-Friday 8:30-5.
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/MICHAEL J METZGER/ Primary Examiner, Art Unit 2183
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