Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-2, 15-16 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Jain et al. (US 12,306,246), hereinafter Jain, in view of Huang et al. (US 7,729,884), hereinafter Huang.
Regarding claim 1, Jain teaches a device configured to operate in functional and diagnostic modes (Jain, Fig. 5 & Fig. 8, col. 7, lines 30-47 teach a circuit having two modes: “scan mode” and “functional mode”), the device comprising: an input terminal configured to receive test pattern data provided by a diagnostic software tool (Jain, Fig. 5 & Fig. 10; col. 7, line 17 through col. 8, line 17; col. 10, lines 31-65 teach a scan input signal SCAN_IN receiving test patterns, a test tool that generates test patterns, and test patterns being shifted into the scan chain through the SCAN_IN); an output terminal configured to provide diagnostic output data (Jain, Fig. 5; col. 7, line 35 through col. 8, line 17 teach a scan output SCAN_OUT that outputs a response and the output is compared against expected results to determine faults); a scan chain connected between the input terminal and the output terminal (Jain, Fig. 5; col. 7, line 17 through col. 8, line 17; Fig 5 teaches scan chain 500 extending between SCAN_IN and SCAN_OUT), the scan chain including: a plurality of sequential elements connected in series and grouped into a plurality of segments (Jain, Fig. 5, first segment 502, second segment 504, and serially connected flip-flops; col. 7, line 17 through col. 8, line 17); and a diagnostic hardware circuit including a plurality of circuit components, each connected to one sequential element of a respective segment (Jain, Fig. 5, multiplexers 506, 508, & 510; col. 7, lines 15-18, “Scan chain 500 includes a first segment 502, a second segment 504, a start-point multiplexer 506, a second multiplexer 508, and an end-point multiplexer 510”); and the test pattern data is serially shifted through the scan chain (Jain, Fig. 5; col. 4-col. 8 teach serially shifting test patterns through the scan chain during “Scan mode” and shifting resulting responses out for comparison); and a device circuit connected to the scan chain and configured to perform one or more circuit functions (Jain, Figs. 2-4; col. 4-6 teach combinational logic 208 connected to the scan chains) and to generate functional data that is sequentially shifted through the scan chain during the functional mode (Jain, col. 4-5 teach functional logic that produces outputs and the scan chain capturing responses after functional operation).
Jain fails to teach wherein: the diagnostic hardware circuit is configured to identify a defective segment of the scan chain during the diagnostic mode, and serially shifting test pattern data through the scan chain in order to isolate the faulty sequential element of the defective segment during the diagnostic mode.
However, Huang, in an analogous art, teaches wherein: the diagnostic hardware circuit is configured to identify a defective segment of the scan chain during the diagnostic mode (Huang, col. 3-4 teach identifying a range of suspect scan cells in a selected scan chain, determining which portion of the scan chain contains a fault, and using observed scan responses to localize the fault before identifying the exact scan cell), and serially shifting test pattern data through the scan chain in order to isolate the faulty sequential element of the defective segment during the diagnostic mode (Huang, col. 3-4).
Jain and Huang are both considered to be analogous to the claimed invention because both are in the same field of scan chain configurations.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified Jain’s segmented scan chain architecture to incorporate the teachings of Huang by including the functionality of identifying a suspect range or segment within the scan chain.
The suggestion/motivation for doing so would be to improve fault isolation by reducing the diagnostic search area of a scan chain, and improving diagnostic efficiency.
Regarding claim 2, the combination of Jain in view of Huang teaches the device of claim 1, wherein the sequential element is the first sequential element (Jain, Fig. 5 teaches multiplexers placed at the beginning and end of the respective segments; the start-point multiplexer 506 feeds the first sequential element of first segment 502, while second multiplexer 508 feeds the first sequential element of second segment 504; col. 7, lines 17-27 and 47-55).
Regarding claim 15, Jain teaches a method for diagnosing faults in a device (Jain teaches a method of diagnosing faults in an integrated circuit that uses segmented scan chains and diagnostic testing), the method comprising: wherein the scan chain includes: a plurality of sequential elements grouped into segments (Jain, Fig. 5, first segment 502, second segment 504, and serially connected flip-flops; col. 7, line 17 through col. 8, line 17); and a diagnostic hardware circuit including a plurality of circuit components, each connected to a first sequential element of a respective segment (Jain, Fig. 5, multiplexers 506, 508, & 510; col. 7, lines 15-18, “Scan chain 500 includes a first segment 502, a second segment 504, a start-point multiplexer 506, a second multiplexer 508, and an end-point multiplexer 510”); serially shifting test pattern data through the scan chain (Jain, Fig. 5; col. 4-col. 8 teach serially shifting test patterns through a scan input signal SCAN_IN, serially shifting responses out through a scan output signal SCAN_OUT, and fault conditions are determined by comparing observed and expected responses).
Jain fails to teach performing a coarse-grain diagnosis on a scan chain of the device to identify a defective segment and performing a fine-grain diagnosis on the identified defective segment to pinpoint one or more faulty sequential elements of the defective segment.
However, Huang, in an analogous art, teaches performing a coarse-grain diagnosis on a scan chain of the device to identify a defective segment (Huang, col. 3-4 teach performing an initial [coarse] diagnosis to determine a suspect range [suspect scan-chain segment] before performing finer diagnosis to isolate the defective scan cell) and performing a fine-grain diagnosis on the identified defective segment to pinpoint one or more faulty sequential elements of the defective segment (Huang, col. 3-4 teach refining diagnosis after the defective segment [suspect range] has been identified, and narrowing the diagnosis from the defective segment to individual scan cells).
Jain and Huang are both considered to be analogous to the claimed invention because both are in the same field of scan chain configurations.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified Jain’s segmented scan chain architecture to incorporate the teachings of Huang by including the functionality of performing coarse-grain and fine-grain diagnostics on identified defective segments.
The suggestion/motivation for doing so would be to improve fault isolation by reducing the diagnostic search area of a scan chain, and improving diagnostic efficiency.
Regarding claim 16, the combination of Jain in view of Huang teaches the method of claim 15, wherein performing the coarse-grain diagnosis includes serially shifting first test pattern data through the scan chain and performing the fine-grain diagnosis includes serially shifting second test pattern data through the scan chain (Huang, col. 3-4 teach performing an initial [coarse] diagnosis to determine a suspect range [suspect scan-chain segment] before performing finer diagnosis to isolate the defective scan cell and refining diagnosis after the defective segment [suspect range] has been identified, and narrowing the diagnosis from the defective segment to individual scan cells; col. 23 teaches additional diagnostic patterns being generated and shifted through the scan chain to further isolate the fault).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the combination of Jain to incorporate the teachings of Huang by including the functionality of using different test patterns for the coarse-grain and fine-grain diagnostic operations.
The suggestion/motivation for doing so would be to improve fault localization while avoiding diagnostic complexity.
Regarding claim 18, the combination of Jain in view of Huang teaches the method of claim 15, further comprising serially shifting functional data through the scan chain (Jain, col. 4-5 teach functional logic that produces outputs and the scan chain capturing responses after functional operation).
Claims 3-7 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Jain in view of Huang, as applied to claims 1 and 15 above, and further in view of Huang et al. (US 2020/0333398), hereinafter Huang-398.
Regarding claim 3, the combination of Jain in view of Huang teaches the device of clam 1, but fails to teach wherein: the diagnostic hardware circuit is configured to diagnose a stuck-at-1 fault in one or more sequential elements of the scan chain during the diagnostic mode; a test pattern data includes a sequence of logical lows is serially shifted through the scan chain; the expected output pattern is compared with the actual output pattern at the output terminal; and a discrepancy between the expected and actual output patterns indicates the presence of a stuck-at-1 fault in one or more sequential elements.
However, Huang-398, in an analogous art, teaches wherein: the diagnostic hardware circuit is configured to diagnose a stuck-at-1 fault in one or more sequential elements of the scan chain during the diagnostic mode; a test pattern data includes a sequence of logical lows is serially shifted through the scan chain; the expected output pattern is compared with the actual output pattern at the output terminal; and a discrepancy between the expected and actual output patterns indicates the presence of a stuck-at-1 fault in one or more sequential elements (Huang-398, para. [0011], lines 2-9, “The method includes: loading a scan cell network with one or more scan chain patterns; unloading the scan cell network to collect scan chain test data; analyzing the scan chain test data in order to identify a stuck-at fault in a global signal in the scan cell network; and responsive to the analysis, identifying whether there is the stuck-at fault in the global signal in the scan cell network”; para. [0108], lines 19-22, “Likewise, to test for defect behavior for stuck-at-I , the system may then apply two U-turn patterns such as LR0000 ... and RL0000 ...Both U-turn patterns will fail as if two stuck-at-1 faults are at the both ends of this scan chain”).
Jain, Huang, and Huang-398 are considered to be analogous to the claimed invention because they are in the same field of scan chain configurations.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the combination of Jain in view of Huang, to incorporate the teachings of Huang-398 by including the functionality of a stuck-at-1 diagnostic pattern.
The suggestion/motivation for doing so would be to identify scan cells incapable of assuming the applied logical low state.
Regarding claim 4, the combination of Jain in view of Huang, further in view of Huang-398, teaches the device of claim 1, wherein: the diagnostic hardware circuit is configured to diagnose a transition delay fault in one or more sequential elements of the scan chain during the diagnostic mode; a test pattern data is serially shifted through the scan chain to induce a rising transition into the scan chain; the expected transitions are captures and compared with the actual transitions at the output terminal; and it is determined whether a sequential element exhibits a delayed response, indicating a transition delay fault (Huang-398, para. [0081], lines 1-5, “Alternatively, or in addition to identifying stuck-at faults, the DDYA methodology may identify timing faults on the scan paths. Timing faults may include any one, any combination, or all of: transition fault; delay fault; or hold time fault”; Huang-398 also teaches, applying diagnostic scan patterns, shifting transition values through the scan cells, analyzing the resulting error values, and identifying timing fault types and fault locations).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the combination of Jain in view of Huang, to incorporate the teachings of Huang-398 by including the functionality of using a rising-transition pattern to diagnose a slow-to-rise transition fault.
The suggestion/motivation for doing so would be to test whether an affected element transitions from a logical low to a logical high within a required timing interval.
Regarding claim 5, the combination of Jain in view of Huang, further in view of Huang-398, teaches the device of claim 1, wherein: the diagnostic hardware circuit is configured to diagnose a stuck-at-0 fault in one or more sequential elements of the scan chain during the diagnostic mode; a test pattern data includes a sequence of logical highs is serially shifted through the scan chain; the expected output pattern is compared with the actual output pattern at the output terminal; and a discrepancy between the expected and actual output patterns indicates the presence of a stuck-at-0 fault in one or more sequential elements (Huang-398, para. [0090] teaches patterns containing logical ones for testing behavior corresponding to stuck-at-0 faults).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the combination of Jain in view of Huang, to incorporate the teachings of Huang-398 by including the functionality of using a logical-high stuck-at-0 diagnostic pattern.
The suggestion/motivation for doing so would be to identify scan cells incapable of assuming the applied logical high state.
Regarding claim 6, the combination of Jain in view of Huang, further in view of Huang-398, teaches the device of claim 1, wherein: the diagnostic hardware circuit is configured to diagnose a transition delay fault in one or more sequential elements of the scan chain during the diagnostic mode; a test pattern data is serially shifted through the scan chain to induce a falling transition into the scan chain; the expected transitions are captures and compared with the actual transitions at the output terminal; and it is determined whether a sequential element exhibits a delayed response, indicating a transition delay fault (Huang-398, para. [0081], lines 1-5, “Alternatively, or in addition to identifying stuck-at faults, the DDYA methodology may identify timing faults on the scan paths. Timing faults may include any one, any combination, or all of: transition fault; delay fault; or hold time fault”; Huang-398 also teaches, applying diagnostic scan patterns, shifting transition values through the scan cells, analyzing the resulting error values, and identifying timing fault types and fault locations).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the combination of Jain in view of Huang, to incorporate the teachings of Huang-398 by including the functionality of using a failing-transition pattern.
The suggestion/motivation for doing so would be to test whether an affected element transitions from a logical high to a logical low within a required timing interval, identifying a slow-to-fall transition-delay fault.
Regarding claim 7, the combination of Jain in view of Huang, further in view of Huang-398, teaches the device of claim 1, wherein the scan chain is configured to switch between functional and diagnostic modes in response to a select signal (Huang-398, para. [0065] teaches that the scan cells are dual-purpose state elements operating in functional/mission mode and scan mode, and the use of a multiplexer to switch between the modes).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the combination of Jain in view of Huang, to incorporate the teachings of Huang-398 by including the functionality of switching between functional and diagnostic modes in response to a select signal.
The suggestion/motivation for doing so would be to allow the same scan-chain circuitry to support both normal operation and diagnostic testing.
Regarding claim 17, the combination of Jain in view of Huang teaches the method of claim 15, but fails to teach wherein performing the coarse-grain diagnosis includes serially shifting first test pattern data from a first sequential element to a last sequential element of the scan chain and performing the fine-grain diagnosis includes serially shifting second test pattern data from the last sequential element to the first sequential element.
However, Huang-398 teaches wherein performing the coarse-grain diagnosis includes serially shifting first test pattern data from a first sequential element to a last sequential element of the scan chain and performing the fine-grain diagnosis includes serially shifting second test pattern data from the last sequential element to the first sequential element (Huang-398, Figs. 2A-2B & 18A-18C; para. [0085]-[0087], [0130]-[0135]; para. [0087], lines 1-4, “In one or some embodiments, a bidirectional scan chain architecture may be used in which the scan chain performs both forward and backward scan shift to diagnose scan faults”; para. [0112]-[0116 teaches performing initial U-turn tests, analyzing the results, performing additional U-turn or Z-turn tests, and identifying the defect location from the resulting error positions).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the combination of Jain in view of Huang, to incorporate the teachings of Huang-398 by including the functionality of performing a second diagnostic operation.
The suggestion/motivation for doing so would be to examine scan responses from opposite directions to provide additional fault information and improve diagnostic resolution.
Claims 8-14 and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Jain, in view of Huang-398.
Regarding claim 8, Jain teaches a device configured to operate in functional and diagnostic modes (Jain, Fig. 5 & Fig. 8, col. 7, lines 30-47 teach a circuit having two modes: “scan mode” and “functional mode”), the device comprising: an input terminal configured to receive test pattern data (Jain, Fig. 5 & Fig. 10; col. 7, line 17 through col. 8, line 17; col. 10, lines 31-65 teach a scan input signal SCAN_IN receiving test patterns, a test tool that generates test patterns, and test patterns being shifted into the scan chain through the SCAN_IN); an output terminal configured to provide diagnostic output data (Jain, Fig. 5; col. 7, line 35 through col. 8, line 17 teach a scan output SCAN_OUT that outputs a response and the output is compared against expected results to determine faults); plurality of segments include a first segment and a second segment that follows the first segment (Jain, Fig. 5, first segment 502, second segment 504, and serially connected flip-flops; col. 7, line 17 through col. 8, line 17); and a diagnostic hardware circuit including: a plurality of circuit components, each connected to one sequential element of a respective segment (Jain, Fig. 5, multiplexers 506, 508, & 510; col. 7, lines 15-18, “Scan chain 500 includes a first segment 502, a second segment 504, a start-point multiplexer 506, a second multiplexer 508, and an end-point multiplexer 510”); and a feedback loop connecting an output of the second segment to an input of the first segment (Jain, Fig. 5 teaches a routing path from the output side of second segment 504 back to start-point multiplexer 506, which supplies first segment 502; col. 8, lines 11-17 teaches the output of second segment 504 being forwarded to the input of first segment 502;); and a device circuit connected to the scan chain and configured to perform one or more circuit functions (Jain, Figs. 2-4; col. 4-6 teach combinational logic 208 connected to the scan chains) and to generate functional data that is sequentially shifted through the scan chain during the functional mode (Jain, col. 4-5 teach functional logic that produces outputs and the scan chain capturing responses after functional operation).
Jain fails to teach a bi-directional scan chain connected between the input terminal and the output terminal, the bi-directional scan chain including: a plurality of sequential elements connected in series and grouped into a plurality of segments, the diagnostic hardware circuit is configured to perform: a forward-shift diagnosis to propagate the test pattern data from a first sequential element to a last sequential element of the scan chain to identify a defective segment of the scan chain during the diagnostic mode, and a backward-shift diagnosis to propagate the test pattern data from the last sequential element to the first sequential element to isolate the faulty sequential element of the defective segment during the diagnostic mode.
However, Huang-398, in an analogous art, teaches a bi-directional scan chain connected between the input terminal and the output terminal, the bi-directional scan chain including: a plurality of sequential elements connected in series and grouped into a plurality of segments, the diagnostic hardware circuit is configured to perform: a forward-shift diagnosis to propagate the test pattern data from a first sequential element to a last sequential element of the scan chain to identify a defective segment of the scan chain during the diagnostic mode, and a backward-shift diagnosis to propagate the test pattern data from the last sequential element to the first sequential element to isolate the faulty sequential element of the defective segment during the diagnostic mode (Huang-398, Figs. 2A-2B & 18A-18C; para. [0085]-[0087], [0130]-[0135]; para. [0087], lines 1-4, “In one or some embodiments, a bidirectional scan chain architecture may be used in which the scan chain performs both forward and backward scan shift to diagnose scan faults”).
Jain and Huang-398 are both considered to be analogous to the claimed invention because both are in the same field of scan chain configurations.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified Jain’s segmented scan chain architecture to incorporate the teachings of Huang by including the functionality of reversible scan-chain diagnostic technique with reversible fault diagnosis.
The suggestion/motivation for doing so would be to improve fault isolation of a defective scan cell.
Claim 9 is a device with limitations similar to the device of claim 2, and is rejected under the same rationale.
Regarding claim 10, the combination of Jain in view of Huang-398 teaches the device of clam 8, wherein: the forward-shift diagnosis is configured to identify a defective segment of the scan chain (Huang-398, para. [0087], lines 1-4, “In one or some embodiments, a bidirectional scan chain architecture may be used in which the scan chain performs both forward and backward scan shift to diagnose scan faults”); a test pattern data is serially shifted from the first sequential element to the last sequential element of the scan chain; the output terminal captures the resulting response of the scan chain; the expected output pattern is compared with the actual output pattern to detect a discrepancy (Jain, Fig. 5; col. 4-col. 8 teach serially shifting test patterns through a scan input signal SCAN_IN, serially shifting responses out through a scan output signal SCAN_OUT, and fault conditions are determined by comparing observed and expected responses); and a defective segment is identified when the discrepancy indicates a deviation from the expected propagation of the test pattern data through the scan chain (Jain teaches segmented scan-chain architecture, while Huang-398 teaches identifying the location or portion of the chain that contains the fault; once Huang-398’s detected location is correlated with Jain’s segment boundaries, the defective segment is identified).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified Jain to incorporate the teachings of Huang-398 by including the functionality of forward-shift diagnostics.
The suggestion/motivation for doing so would be to identify the defective segment and reduce the portion of the scan chain that requires further diagnosis.
Regarding claim 11, the combination of Jain in view of Huang-398 teaches the device of claim 8, wherein: the backward-shift diagnosis is performed after identifying a defective segment; a test pattern data is serially shifted in reverse order, from the last sequential element to the first sequential element of the scan chain; the diagnostic hardware circuit isolates the faulty sequential element within the defective segment by analyzing the response at the output terminal; and a sequential element is determined to be faulty if its actual output response deviates from the expected test pattern data during backward shifting (Huang-398, Figs. 2A-2B & 18A-18C; para. [0085]-[0087], [0130]-[0135]; para. [0087], lines 1-4, “In one or some embodiments, a bidirectional scan chain architecture may be used in which the scan chain performs both forward and backward scan shift to diagnose scan faults”; para. [0112]-[0116 teaches performing initial U-turn tests, analyzing the results, performing additional U-turn or Z-turn tests, and identifying the defect location from the resulting error positions).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified Jain to incorporate the teachings of Huang-398 by including the functionality of backward-shift diagnostics after identifying a defective segment.
The suggestion/motivation for doing so would be to allow the faulty sequential element within the defective segment to be isolated.
Regarding claim 12, the combination of Jain in view of Huang-398 teaches the device of claim 8, wherein the diagnostic hardware circuit is configured to diagnose stuck-at faults (Huang-398, para. [0081], lines 1-5, “Alternatively, or in addition to identifying stuck-at faults, the DDYA methodology may identify timing faults on the scan paths. Timing faults may include any one, any combination, or all of: transition fault; delay fault; or hold time fault”).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified Jain to incorporate the teachings of Huang-398 by including the functionality of stuck-at fault diagnosis.
The suggestion/motivation for doing so would be to identify elements that remain stuck at an incorrect logical state.
Regarding claim 13, the combination of Jain in view of Huang-398 teaches the device of claim 8, wherein the diagnostic hardware circuit is configured to diagnose transition delay faults (Huang-398, para. [0081], lines 1-5, “Alternatively, or in addition to identifying stuck-at faults, the DDYA methodology may identify timing faults on the scan paths. Timing faults may include any one, any combination, or all of: transition fault; delay fault; or hold time fault”).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified Jain to incorporate the teachings of Huang-398 by including the functionality of transition delay fault diagnosis.
The suggestion/motivation for doing so would be to identify elements that exhibit delayed responses.
Claim 14 is a device with limitations similar to the device of claim 7, and is rejected under the same rationale.
Claim 19 is a method with limitations similar to the device of claim 12, and is rejected under the same rationale.
Claim 20 is a method with limitations similar to the device of claim 13, and is rejected under the same rationale.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Cheng et al. (US 11,408,938) teaches bidirectional scan chains and forward/reverse shifting.
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/G.V.B./Examiner, Art Unit 2112
/ALBERT DECADY/Supervisory Patent Examiner, Art Unit 2112
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