DETAILED ACTION
The action is responsive to the following communications: the Application filed April 11, 2025. This application is a CON of 18/506,213.
Claims 1-20 are pending. Claims 1, 13 and 17 are independent.
Notice of Pre-AIA or AIA Status
The present application is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on November 10, 2023 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP §§ 706.02(l)(1) - 706.02(l)(3) for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of US Patent No. 12,300,312. Although the claims at issue are not identical, they are not patentably distinct from each other.
Instant Application
US Patent 12,300,312
Comment
Claim 1. A device comprising:
a voltage supply line coupled to a bit line and a complementary bit line; and
a circuit configured to charge the bit line by:
transferring a charge from the voltage supply line to the bit line while the voltage supply line is electrically isolated from a voltage source and the complementary bit line.
Claim 1. A device comprising:
a bit line and a complementary bit line coupled to a memory cell;
a voltage supply line coupled to the memory cell; and
a circuit configured to charge the bit line by:
charging the voltage supply line to a first voltage level while the voltage supply line is electrically isolated from the bit line; and
transferring a charge from the voltage supply line to the bit line while the voltage supply line is electrically isolated from a voltage source and the complementary
bit line.
Note footnote1
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-12 and 17-20 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Claims 1 and 17 are device claims. However, claims 1 and 17 also claim using the apparatus, such as charging, transferring and storing without additional limitations which focus on the capabilities of the apparatus. A single claim which claims both an apparatus and using the apparatus is indefinite. See MPEP 2173.05(p). Clarification is required.
Claims 2-12 and 18-20 are rejected to as being dependent upon a rejected base claims 1 and 14, respectively.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of AIA 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-7, 9 and 13-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ito (US 4,893,278).
Regarding independent claims 1, 13 and 17, Ito discloses a device (see FIG. 3) comprising:
a voltage supply line (drain node of Q5 or Q6, i.e., supplying bit line voltage) coupled to a bit line (D0 or D1) and a complementary bit line (/D0 or /D1); and
a circuit configured to charge the bit line by:
transferring a charge from the voltage supply line to the bit line while the voltage supply line is electrically isolated from a voltage source and the complementary bit line (see FIG. 4: øpc = “L” and øeq1 = “H”) (see FIG. 4 along with FIG. 3, and accompanying disclosure).
Regarding claim 2, which depends from claim 1, Ito discloses the circuit is further configured to electrically isolate the voltage supply line from the bit line by opening a second switch (see FIG. 3: one of Q8-Q11).
Regarding claim 3, which depends from claim 1, Ito discloses the circuit is further configured to transfer the portion of the charge from the voltage supply line to the bit line by closing a second switch (see FIG. 3: one of Q8-Q11).
Regarding claims 4-5, which depends from claim 1, Ito discloses the circuit is further configured to charge the voltage supply line while the voltage supply line is electrically isolated from the bit line by opening a second switch and closing a first switch; and the first switch is coupled between the voltage supply line and the voltage source (see FIG. 3: one of Q8-Q11, Q5).
Regarding claims 6-7, which depends from claim 1, Ito discloses a third switch (one of Q8-Q11) coupled between the bit line or the voltage supply line and the complementary bit line; and a gate terminal of the second switch and a gate terminal of the third switch are coupled to each other (see FIG. 3).
Regarding claim 9, which depends from claim 1, Ito discloses the circuit is further configured to electrically isolate the voltage supply line from the bit line and the complementary bit line by opening second and third switches (see FIGS. 3-4 and accompanying disclosure).
Regarding claim 14, which depends from claim 13, Ito discloses transferring the charge to the bit line or the complementary bit line includes capacitively storing the charge on the bit line or the complementary bit line, the method further comprising: charging the voltage supply line to the first voltage level by closing a first switch and opening second and third switches; storing the charge on the bit line by opening the second switch; and storing the charge on the complementary bit line by opening the third switch (see e.g., FIGS. 3-4 and accompanying disclosure).
Regarding claim 15, which depends from claim 13, Ito discloses accessing a memory cell using the charge on the bit line, the charge on the complementary bit line, and the charge on the voltage supply line (see e.g., FIGS. 3-4 and accompanying disclosure).
Regarding claim 16, which depends from claim 13, Ito discloses charging the voltage supply line includes charging the voltage supply line to the voltage source (see e.g., FIGS. 3-4 and accompanying disclosure).
Regarding claim 18, which depends from claim 17, Ito discloses the circuit is further configured to charge the voltage supply line while the voltage supply line is electrically isolated from the bit line and the complementary bit line by closing a first switch (e.g., FIG. 3: Q5-Q6).
Regarding claim 19, which depends from claim 17, Ito discloses the circuit is further configured to electrically isolate the voltage supply line from the bit line and the complementary bit line by opening second and third switches (e.g., FIG. 3: Q8-Q11).
Regarding claim 20, which depends from claim 13, Ito discloses the circuit is further configured to access a memory cell using the charge on the voltage supply line (see e.g., FIGS. 3-4 and accompanying disclosure).
Claim Rejections - 35 USC § 103
The following is a quotation of AIA 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 8 and 10-11 are rejected under AIA 35 U.S.C. 103 as being unpatentable over Ito (US 4,893,278).
Regarding claim 8, Ito teaches the limitations of claim 1.
FIG. 3 of Ito does not explicitly disclose the voltage supply line is directly coupled to a memory cell.
However, the virtual voltage supply line directly coupled to a memory cell is a well-known technology for a type of memory for its purpose.
For support, see Ito’s FIGS 5-9 and accompanying disclosure.
It would have been obvious to one of ordinary skill in the art before the effective filing date to utilize virtual supply voltages coupled to memory cells because these conventional technology are well established in the art of the memory devices.
Regarding claims 10-11, Ito teaches the limitations of claim 1.
Ito does not explicitly disclose the circuit is further configured to charge the voltage supply line to the first voltage level by storing a charge in a line capacitor of the voltage supply line; and the circuit is further configured to charge the bit line to the second voltage level by sharing a charge stored in a line capacitor of the voltage supply line with a line capacitor of the bit line.
Instead, Ito discloses charging voltage level to a bit line (see e.g., FIGS 3-4 and accompanying disclosure).
However, charging voltage level to a bit line implies charging bit line capacitor, i.e., charging voltage level to a line capacitor (e.g., parasitic capacitor) of bit line and complementary bit line is a well-known technology for a type of semiconductor memory device for its purpose.
For support, of the above asserted facts, see for example, Reddy (US 5,525,918), FIG. 1: C1-C4.
It would have been obvious to one of ordinary skill in the art before the effective filing date to utilize capacitor for storing charges because these conventional technology are well established in the art of the memory devices.
Claim 12 is rejected under AIA 35 U.S.C. 103 as being unpatentable over Ito (US 4,893,278) in view of Huber (US 2015/0029807).
Regarding claim 12, Ito teaches the limitations of claim 1.
Ito does not explicitly disclose the circuit is further configured to charge the complementary bit line prior to or after the bit line.
Huber teaches the deficiencies in e.g., FIGS. 4-5 and accompanying disclosure, i.e., PRCHB0 for BL and PRCHB1 for BLB.
It would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teaching of Huber to the teaching of Ito such that a memory, as taught by Ito, utilizes cascade charging , as taught by Huber, for the purpose of achieving different charging scheme, thereby minimizing peak to peak current for saving power.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SUNG IL CHO whose telephone number is (571)270-0137. The examiner can normally be reached on M-Th, 7:30AM-5PM; Every other F, 7:30AM-4PM EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Alexander G Sofocleous can be reached on 571-272-0635. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SUNG IL CHO/Primary Examiner, Art Unit 2825
1 Re independent claims 1, 13 and 17, claims of US Patent recites all the claimed limitations. The various dependent claims are anticipated by/obvious in view of the conflicting patent.
Prosecution Insights