DETAILED ACTION
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are pending in the application.
Information Disclosure Statement
The information Disclosure Statement (IDS) Form PTO-1449, filed 04/21/2025, 06/17/2025 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosed therein was considered by the examiner.
Drawings
The drawings submitted on 04/21/2025. These drawings are review and accepted by the examiner.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the claims at issue are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the reference application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO internet Web site contains terminal disclaimer forms which may be used. Please visit http://www.uspto.gov/forms/. The filing date of the application will determine what form should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to http://www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Claims 1-20 are rejected on the ground of nonstatutory obviousness-type double patenting as being unpatentable over claims 1-20 of U.S Patent No. 12,308,078 B2 (‘078). Although the conflicting claims are not identical, they are not patentably distinct from each other because the instant application claims are obvious variants of the ‘078 claims.
US Patent No. 12,308,078 B2
US Patent Application No. 2025/0253004 A1
1. A one-time programmable (OTP) memory, comprising: a plurality of bit lines; a plurality of word lines; and a plurality of memory cells, each memory cell of the plurality of memory cells comprising: a first terminal coupled to a bit line of the plurality of bit lines; a second terminal coupled to a word line of the plurality of word lines; and a selector connected directly to the first terminal and directly to the second terminal and having a threshold voltage that is alterable by an electric current, wherein the OTP memory comprises an information block of a memory device and is configured to store information dedicated to the memory device, and each of the OTP memory and the memory device comprises a three-dimensional cross-point structure including a plurality of first level memory cells and a plurality of second level memory cells vertically stacked on the plurality of first level memory cells, respectively.
2. The OTP memory of claim 1, wherein the OTP memory comprises an eFuse memory of the memory device.
3. The OTP memory of claim 2, wherein the associated memory of the semiconductor device comprises one selector and one resistive element (1S1R) memory cells.
4. The OTP memory of claim 3, wherein a material of the selector of the OTP memory is substantially the same as a material of the selector of the associated memory.
5. The OTP memory of claim 1, wherein the selector comprises one of a diode or an ovonic threshold switch comprising a layer of phase change material.
6. The OTP memory of claim 1, further comprising: a plurality of bit line select switches for selecting a bit line of the plurality of bit lines; a plurality of word line select switches for selecting a word line of the plurality of word lines; and a plurality of sense amplifiers connected to the plurality of bit lines, for sensing a current on the plurality of bit lines, respectively.
7. The OTP memory of claim 1, wherein a cell area of each memory cell in the plurality of memory cells is in a range from 25 nm.sup.2 to 2500 nm.sup.2.
8. The OTP memory of claim 1, wherein the selector comprises: a lower barrier layer; a phase-change material layer on the lower barrier layer; and an upper barrier layer on the phase-change material layer.
9. The OTP memory of claim 1, wherein the first terminal comprises an upper conductive material layer formed on the upper barrier layer, the second terminal comprises a lower conductive material layer, and the lower barrier layer is on the lower conductive material layer.
10. The OTP memory of claim 1, wherein the selector is configured to have a first threshold voltage in a range from 2.5 V to 4.5 V and a second threshold voltage in a range from 0.1 V to 1.8 V.
11. The OTP memory of claim 1, wherein the selector is configured to have a threshold voltage that is decreased from the first threshold voltage to the second threshold voltage by performing a write operation on the selector.
12. The OTP memory of claim 1, wherein the selector is configured to be switched from a logic “0” state to a logic “1” state by performing a write operation on the selector.
13. The OTP memory of claim 1, wherein the first terminal is connected directly to the bit line and the second terminal connected direction to the word line.
14. The OTP memory of claim 1, wherein the selector comprises an ovonic threshold switch (OTS) comprising: a lower barrier layer; phase-change material layer on the lower barrier layer; and an upper barrier layer on the phase-change material layer.
15. The OTP memory of claim 1, wherein the first terminal of the memory cell comprises an upper conductive material layer on the upper barrier layer of the selector, the second terminal of the memory cell comprises a lower conductive material layer and the lower barrier layer of the selector is on the lower conductive material layer.
16. A method of operating a one-time programmable (OTP) memory, the method comprising: providing the OTP memory, wherein the OTP memory includes a plurality of memory cells, each memory cell of the plurality of memory cells comprising: a first terminal coupled to a bit line; a second terminal coupled to a word line; and a selector connected directly to the first terminal and directly to the second terminal, wherein the OTP memory comprises an information block of a memory device and is configured to store information dedicated to the memory device, and each of the OTP memory and the memory device comprises a three-dimensional cross-point structure including a plurality of first level memory cells and a plurality of second level memory cells vertically stacked on the plurality of first level memory cells, respectively; performing a write operation comprising supplying a first write voltage to the first terminal of a selected memory cell and a second write voltage to the second terminal of the selected memory cell so as to decrease a threshold voltage of the selector of the selected memory cell from a first threshold value to a second threshold value, wherein a difference between the first write voltage and the second write voltage is greater than the first threshold value; and performing a read operation comprising supplying a first read voltage to the first terminal and a second read voltage to the second terminal of the selected memory cell, so that a logic state of the selected memory cell is sensible, wherein a difference between the first read voltage and the second read voltage is less than the first threshold value and greater than the second threshold value.
17. The method of claim 16, wherein the performing of the read operation further comprises sensing a current in a bit line of the OTP memory generated by the supplying of the first read voltage to the first terminal and the second read voltage to the second terminal.
18. A semiconductor device comprising: a memory device including a plurality of memory device memory cells, each memory device memory cell of the plurality of memory device memory cells comprising a memory device selector; and a one-time programmable (OTP) memory including a plurality of memory cells, each memory cell of the plurality of memory cells comprising: a first terminal coupled to a bit line; a second terminal coupled to a word line; a selector connected directly to the first terminal and directly to the second terminal and substantially the same as the memory device selector, wherein the OTP memory comprises an information block of the memory device and is configured to store information dedicated to the memory device, and each of the OTP memory and the memory device comprises a three-dimensional cross-point structure including a plurality of first level memory cells and a plurality of second level memory cells vertically stacked on the plurality of first level memory cells, respectively.
19. The semiconductor device of claim 18, wherein the memory device selector comprises a first material and the selector comprises a second material substantially the same as the first material.
20. The semiconductor device of claim 18, wherein each memory device memory cell of the plurality of memory device memory cells further comprises a memory device resistive element connected in series with the memory device selector.
1. A semiconductor device, comprising: a memory device comprising a plurality of memory device memory cells; and a one-time programmable (OTP) memory comprising a plurality of OTP memory cells and configured to store global information for the semiconductor device, wherein the plurality of OTP memory cells comprises one of one selector and one resistive element (1S1R) memory cells or one selector (1S) memory cells and a structure of the plurality of memory device memory cells is substantially the same as a structure of the plurality of OTP memory cells.
2. The semiconductor device of claim 1, wherein the plurality of memory device memory cells comprises one selector and one resistive element (1S1R) memory cells and the plurality of OTP memory cells comprises one selector and one resistive element (1S1R) memory cells.
3. The semiconductor device of claim 2, wherein the OTP memory further comprises: a plurality of bit lines; and a plurality of word lines, and an OTP memory cell of the plurality of OTP memory cells comprises: a first terminal coupled to a bit line of the plurality of bit lines; a second terminal coupled to a word line of the plurality of word lines; a selector between the first terminal and the second terminal and having a threshold voltage that is alterable by an electric current; and a resistive element in series with the selector between the first terminal and the second terminal and having a resistance that is alterable by an electric current.
4. The semiconductor device of claim 3, wherein the resistive element is coupled between the first terminal and the selector, and the selector is coupled between the second terminal and the resistive element.
5. The semiconductor device of claim 3, wherein the resistive element comprises one of a phase change random access memory (PCRAM) data storage material, a resistive random access memory (RRAM) data storage material, a ferroelectric random access memory (FeRAM) data storage material or a conductive bridging random access memory (CBRAM) data storage material.
6. The semiconductor device of claim 3, wherein the selector comprises one of a diode or an ovonic threshold switch comprising a layer of phase change material.
7. The semiconductor device of claim 3, wherein the selector cooperates with the resistive element to store data, and inhibits generation of a leakage current from the OTP memory cell when the OTP memory cell is not selected.
8. The semiconductor device of claim 3, wherein the selector comprises a first plurality of layers, and the resistive element comprises a second plurality of layers that are stacked on the first plurality of layers.
9. The semiconductor device of claim 1, wherein the plurality of memory device memory cells comprises one selector (1S) memory cells and the plurality of OTP memory cells comprises one selector (1S) memory cells.
10. The semiconductor device of claim 9, wherein the OTP memory further comprises: a plurality of bit lines; and a plurality of word lines, and an OTP memory cell of the plurality of OTP memory cells comprises: a first terminal coupled to a bit line of the plurality of bit lines; a second terminal coupled to a word line of the plurality of word lines; and a selector connected directly to the first terminal and directly to the second terminal and having a threshold voltage that is alterable by an electric current.
11. The semiconductor device of claim 1, wherein the OTP memory comprises an eFuse memory of the semiconductor device.
12. The semiconductor device of claim 1, wherein each of the OTP memory and the memory device comprises a three-dimensional cross-point structure including a plurality of first level memory cells and a plurality of second level memory cells vertically stacked on the plurality of first level memory cells, respectively.
13. A memory device, comprising: a plurality of memory blocks comprising a plurality of memory block memory cells; and a one-time programmable (OTP) memory comprising a plurality of OTP memory cells and configured to serve as an information block of the memory device and store information dedicated to the memory device, wherein the plurality of OTP memory cells comprises one of one selector and one resistive element (1S1R) memory cells or one selector (1S) memory cells and a structure of the plurality of memory block memory cells is substantially the same as a structure of the plurality of OTP memory cells.
14. The memory device of claim 13, wherein the plurality of memory block memory cells comprises one selector and one resistive element (1S1R) memory cells and the plurality of OTP memory cells comprises one selector and one resistive element (1S1R) memory cells.
15. The memory device of claim 14, wherein the OTP memory further comprises: a plurality of bit lines; and a plurality of word lines, and an OTP memory cell of the plurality of OTP memory cells comprises: a first terminal coupled to a bit line of the plurality of bit lines; a second terminal coupled to a word line of the plurality of word lines; a selector between the first terminal and the second terminal and having a threshold voltage that is alterable by an electric current; and a resistive element in series with the selector between the first terminal and the second terminal and having a resistance that is alterable by an electric current.
16. The memory device of claim 15, wherein the resistive element comprises one of a phase change random access memory (PCRAM) data storage material, a resistive random access memory (RRAM) data storage material, a ferroelectric random access memory (FeRAM) data storage material or a conductive bridging random access memory (CBRAM) data storage material, and the selector comprises one of a diode or an ovonic threshold switch comprising a layer of phase change material.
17. The memory device of claim 13, wherein the plurality of memory block memory cells comprises one selector (1S) memory cells and the plurality of OTP memory cells comprises one selector (1S) memory cells.
18. The memory device of claim 17, wherein the OTP memory further comprises: a plurality of bit lines; and a plurality of word lines, and an OTP memory cell of the plurality of OTP memory cells comprises: a first terminal coupled to a bit line of the plurality of bit lines; a second terminal coupled to a word line of the plurality of word lines; and a selector connected directly to the first terminal and directly to the second terminal and having a threshold voltage that is alterable by an electric current.
19. The memory device of claim 13, wherein each of the OTP memory and the plurality of memory blocks comprises a three-dimensional cross-point structure including a plurality of first level memory cells and a plurality of second level memory cells vertically stacked on the plurality of first level memory cells, respectively.
20. A method of forming a semiconductor device, the method comprising: forming a memory device comprising a plurality of memory device memory cells; and concurrently with the forming of the memory device, forming a one-time programmable (OTP) memory comprising a plurality of OTP memory cells and configured to store global information for the semiconductor device, wherein the plurality of OTP memory cells comprises one of one selector and one resistive element (1S1R) memory cells or one selector (1S) memory cells and a structure of the plurality of memory device memory cells is substantially the same as a structure of the plurality of OTP memory cells.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, 9, 11 are rejected under both 35 U.S.C. 102(a)(1) as being anticipated by Redaelli (US 10,418,119 B2).
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Regarding Independent Claim 1, Redaelli, for example in Figs. 1-3, discloses a semiconductor device (see for example in Fig. 1 related in Figs. 2-3), comprising: a memory device (e.g., memory device 122; in Fig. 1 related in Figs. 2-3) comprising a plurality of memory device memory cells (e.g., memory cells within array 122b; in Fig. 3B related in Figs. 1-2, 3A, 3C); and a one-time programmable (OTP) memory (e.g., one-time program 130b/130a/130c; in Figs. 3A-3C related in Figs. 1-2) comprising a plurality of OTP memory cells (see for example in Fig. 3B related in Figs. 1-2, 3A, 3C) and configured to store global information for the semiconductor device (implied memory cell’s function; in Fig. 3B related in Figs. 1-2, 3A, 3C), wherein the plurality of OTP memory cells comprises one of one selector and one resistive element (1S1R) memory cells or one selector (1S) memory cells (e.g., phase-change element and transistor; in Fig. 3A related in Figs. 1-2, 3B, 3C) and a structure of the plurality of memory device memory cells is substantially the same as a structure of the plurality of OTP memory cells (see for example in Fig. 3B related in Figs. 1-2, 3A, 3C).
The structure in of the prior art (Redaelli) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
Regarding claim 2, Redaelli, for example n Figs. 1-3, discloses wherein the plurality of memory device memory cells comprises one selector and one resistive element (1S1R) memory cells and the plurality of OTP memory cells comprises one selector and one resistive element (1S1R) memory cells (see for example in Fig. 3B related in Figs. 1-2, 3A, 3C, as discussed above).
Regarding claim 9, Redaelli, for example in Figs. 1-3, discloses wherein the plurality of memory device memory cells comprises one selector (1S) memory cells and the plurality of OTP memory cells comprises one selector (1S) memory cells (see for example in Fig. 3B related in Figs. 1-2, 3A, 3C, as discussed above).
Regarding claim 11, Redaelli, for example in Figs. 1-3, discloses wherein the OTP memory comprises an eFuse memory of the semiconductor device (see for example in Fig. 3 related in Figs. 1-2, as discussed above).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 3-8, 10, 12-20 are rejected under 35 U.S.C. 103 as being unpatentable over Redaelli (US 10,418,119 B2) in view of Nardi (US 10,290,348 B1).
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Regarding claim 3, Redaelli, for example in Figs. 1-3, discloses the claimed invention as discussed above. However, Redaelli is silent to name or shown a bit line of the plurality of bit lines; and a plurality of word lines.
In the same field of endeavor, Nardi, for example in Figs. 1-7, discloses bit line of the plurality of bit lines (e.g., LBL; in Fig. 4A related in Figs. 1-3, 5-7); and a plurality of word lines (e.g., WL; in Fig. 4A related in Figs. 1-3, 5-7).
It would have been obvious before the effective filling date of the claimed invention was made to a person having ordinary skill in the art to modify the teaching of Redaelli such as apparatuses and/or method for operating a memory cells as an anti-fuse (see for example in Figs. 1-3 of Redaelli) by incorporating the teaching of Nardi such as write-one read-many amorphous chalcogenide-based memory (see for example in Figs. 1-7 of Nardi). In order to provide a memory device having the chalcogenide-based memory may be written as a one-time programmable memory in which forming operations are performed on only memory cells that are to be programmed to store a first binary value (e.g., binary “1” data values) and not performed on other memory cells that are to store a second binary value different from the first binary value (e.g., binary “0” data values) (Nardi, see abstract).
Regarding claim 4, the above Redaelli/Nardi, combination discloses wherein the resistive element is coupled between the first terminal and the selector, and the selector is coupled between the second terminal and the resistive element (see for example see for example in Fig. 3B related in Figs. 1-2, 3A, 3C of Redaelli and also see in Fig. 4A related in Figs. 1-3, 5-7 of Nardi, as discussed above).
Regarding claim 5, the above Redaelli/Nardi, combination discloses wherein the resistive element comprises one of a phase change random access memory (PCRAM) data storage material, a resistive random access memory (RRAM) data storage material, a ferroelectric random access memory (FeRAM) data storage material or a conductive bridging random access memory (CBRAM) data storage material (see for example see for example in Fig. 3B related in Figs. 1-2, 3A, 3C of Redaelli and also see in Fig. 4A related in Figs. 1-3, 5-7 of Nardi, as discussed above).
Regarding claim 6, the above Redaelli/Nardi, combination discloses wherein the selector comprises one of a diode or an ovonic threshold switch comprising a layer of phase change material (see for example see for example in Fig. 3B related in Figs. 1-2, 3A, 3C of Redaelli and also see in Fig. 4A related in Figs. 1-3, 5-7 of Nardi, as discussed above).
Regarding claim 7, the above Redaelli/Nardi, combination discloses wherein the selector cooperates with the resistive element to store data, and inhibits generation of a leakage current from the OTP memory cell when the OTP memory cell is not selected (see for example see for example in Fig. 3B related in Figs. 1-2, 3A, 3C of Redaelli and also see in Fig. 4A related in Figs. 1-3, 5-7 of Nardi, as discussed above). Also, the structure in of the prior art (Redaelli/Nardi) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
Regarding claim 8, the above Redaelli/Nardi, combination discloses wherein the selector comprises a first plurality of layers, and the resistive element comprises a second plurality of layers that are stacked on the first plurality of layers (see for example see for example in Fig. 3B related in Figs. 1-2, 3A, 3C of Redaelli and also see in Fig. 4A related in Figs. 1-3, 5-7 of Nardi, as discussed above).
Regarding claim 10, the above Redaelli/Nardi, combination discloses wherein the OTP memory further comprises: a plurality of bit lines; and a plurality of word lines, and an OTP memory cell of the plurality of OTP memory cells comprises: a first terminal coupled to a bit line of the plurality of bit lines; a second terminal coupled to a word line of the plurality of word lines; and a selector connected directly to the first terminal and directly to the second terminal and having a threshold voltage that is alterable by an electric current (see for example see for example in Fig. 3B related in Figs. 1-2, 3A, 3C of Redaelli and also see in Fig. 4A related in Figs. 1-3, 5-7 of Nardi, as discussed above). Also, the structure in of the prior art (Redaelli/Nardi) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
Regarding claim 12, the above Redaelli/Nardi, combination discloses wherein each of the OTP memory and the memory device comprises a three-dimensional cross-point structure including a plurality of first level memory cells and a plurality of second level memory cells vertically stacked on the plurality of first level memory cells, respectively (see for example see for example in Fig. 3B related in Figs. 1-2, 3A, 3C of Redaelli and also see in Fig. 4A related in Figs. 1-3, 5-7 of Nardi, as discussed above).
Regarding Independent Claim 13, Redaelli, for example in Figs. 1-3, discloses a memory device (see for example in Fig. 1 related in Figs. 2-3), comprising a plurality of memory block memory cells; and a one-time programmable (OTP) memory comprising a plurality of OTP memory cells (see for example in Fig. 3B related in Figs. 1-2, 3A, 3C) and configured to serve as an information block of the memory device and store information dedicated to the memory device (implied memory cell’s function; in Fig. 3B related in Figs. 1-2, 3A, 3C), wherein the plurality of OTP memory cells comprises one of one selector and one resistive element (1S1R) memory cells or one selector (1S) memory cells (e.g., phase-change element and transistor; in Fig. 3A related in Figs. 1-2, 3B, 3C) and a structure of the plurality of memory block memory cells is substantially the same as a structure of the plurality of OTP memory cells (see for example in Fig. 3B related in Figs. 1-2, 3A, 3C).
However, Redaelli is silent with regard to a plurality of memory blocks comprising a plurality of memory block memory cells.
In the same field of endeavor, Nardi, for example in Figs. 1-7, discloses a plurality of memory blocks comprising a plurality of memory block memory cells (e.g., Memory Bays 330/331; in Figs. 1A, 1C, 1D related in Figs. 2-7).
It would have been obvious before the effective filling date of the claimed invention was made to a person having ordinary skill in the art to modify the teaching of Redaelli such as apparatuses and/or method for operating a memory cells as an anti-fuse (see for example in Figs. 1-3 of Redaelli) by incorporating the teaching of Nardi such as write-one read-many amorphous chalcogenide-based memory (see for example in Figs. 1-7 of Nardi). In order to provide a memory device having the chalcogenide-based memory may be written as a one-time programmable memory in which forming operations are performed on only memory cells that are to be programmed to store a first binary value (e.g., binary “1” data values) and not performed on other memory cells that are to store a second binary value different from the first binary value (e.g., binary “0” data values) (Nardi, see abstract).
Regarding claim 14, the above Redaelli/Nardi, combination discloses wherein the plurality of memory block memory cells comprises one selector and one resistive element (1S1R) memory cells and the plurality of OTP memory cells comprises one selector and one resistive element (1S1R) memory cells (see for example see for example in Fig. 3B related in Figs. 1-2, 3A, 3C of Redaelli and also see in Fig. 4A related in Figs. 1-3, 5-7 of Nardi, as discussed above).
Regarding claim 15, the above Redaelli/Nardi, combination discloses wherein the OTP memory further comprises: a plurality of bit lines; and a plurality of word lines, and an OTP memory cell of the plurality of OTP memory cells comprises: a first terminal coupled to a bit line of the plurality of bit lines; a second terminal coupled to a word line of the plurality of word lines; a selector between the first terminal and the second terminal and having a threshold voltage that is alterable by an electric current; and a resistive element in series with the selector between the first terminal and the second terminal and having a resistance that is alterable by an electric current (see for example see for example in Fig. 3B related in Figs. 1-2, 3A, 3C of Redaelli and also see in Fig. 4A related in Figs. 1-3, 5-7 of Nardi, as discussed above).
Regarding claim 16, the above Redaelli/Nardi, combination discloses wherein the resistive element comprises one of a phase change random access memory (PCRAM) data storage material, a resistive random access memory (RRAM) data storage material, a ferroelectric random access memory (FeRAM) data storage material or a conductive bridging random access memory (CBRAM) data storage material, and the selector comprises one of a diode or an ovonic threshold switch comprising a layer of phase change material (see for example see for example in Fig. 3B related in Figs. 1-2, 3A, 3C of Redaelli and also see in Fig. 4A related in Figs. 1-3, 5-7 of Nardi, as discussed above).
Regarding claim 17, the above Redaelli/Nardi, combination discloses wherein the plurality of memory block memory cells comprises one selector (1S) memory cells and the plurality of OTP memory cells comprises one selector (1S) memory cells (see for example see for example in Fig. 3B related in Figs. 1-2, 3A, 3C of Redaelli and also see in Fig. 4A related in Figs. 1-3, 5-7 of Nardi, as discussed above).
Regarding claim 18, the above Redaelli/Nardi, combination discloses wherein the OTP memory further comprises: a plurality of bit lines; and a plurality of word lines, and an OTP memory cell of the plurality of OTP memory cells comprises: a first terminal coupled to a bit line of the plurality of bit lines; a second terminal coupled to a word line of the plurality of word lines; and a selector connected directly to the first terminal and directly to the second terminal and having a threshold voltage that is alterable by an electric current (see for example see for example in Fig. 3B related in Figs. 1-2, 3A, 3C of Redaelli and also see in Fig. 4A related in Figs. 1-3, 5-7 of Nardi, as discussed above). Also, the structure in of the prior art (Redaelli/Nardi) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
Regarding claim 19, the above Redaelli/Nardi, combination discloses wherein each of the OTP memory and the plurality of memory blocks comprises a three-dimensional cross-point structure including a plurality of first level memory cells and a plurality of second level memory cells vertically stacked on the plurality of first level memory cells, respectively (see for example see for example in Fig. 3B related in Figs. 1-2, 3A, 3C of Redaelli and also see in Fig. 4A related in Figs. 1-3, 5-7 of Nardi, as discussed above).
Regarding Independent Claim 20, Redaelli, for example in Figs. 1-3, discloses a method of forming (see Col. 8, lines 28+) a semiconductor device (see for example in Fig. 1 related in Figs. 2-3), the method comprising: forming a memory device (e.g., memory device 122; in Fig. 1 related in Figs. 2-3) comprising a plurality of memory device memory cells (e.g., memory cells within array 122b; in Fig. 3B related in Figs. 1-2, 3A, 3C); and concurrently with the forming of the memory device, forming a one-time programmable (OTP) memory (e.g., one-time program 130b/130a/130c; in Figs. 3A-3C related in Figs. 1-2) comprising a plurality of OTP memory cells and configured to store global information for the semiconductor device (implied memory cell’s function; in Fig. 3B related in Figs. 1-2, 3A, 3C), wherein the plurality of OTP memory cells comprises one of one selector and one resistive element (1S1R) memory cells or one selector (1S) memory cells (e.g., phase-change element and transistor; in Fig. 3A related in Figs. 1-2, 3B, 3C) and a structure of the plurality of memory device memory cells is substantially the same as a structure of the plurality of OTP memory cells (see for example in Fig. 3B related in Figs. 1-2, 3A, 3C).
The structure in of the prior art (Redaelli) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
Conclusion
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/THA-O H BUI/Primary Examiner, Art Unit 2825 09/30/2026
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