DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 1-7 and 14-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over corresponding claims 1-20 of U.S. Patent No. US 12,320,839 B2 in view of JP 3621384 B2.
A comparison of the claims is presented in the following table with exact correspondence in bold face.
Instant Application
U.S. Patent No. US 12,320,839 B2
1. A method for performing an asynchronous automatic test-pattern generation (ATPG) by an ATPG machine, the method comprising:
generating a set of test patterns;
detecting one or more faults associated with the set of test patterns;
receiving information relating to undetected faults; and
responsive to a degree of staleness of a fault state of the ATPG machine determined based at least on the information relating to the undetected faults,
updating the fault state of the ATPG machine.
1. A method for performing an asynchronous automatic test-pattern generation (ATPG) by an ATPG machine, the method comprising:
generating a set of test patterns; detecting one or more faults associated with the set of test patterns;
communicating information relating to the detected one or more faults to an ATPG manager, the ATPG manager configured to communicate with one or more other ATPG machines; and
based on a degree of staleness of a fault state of the ATPG machine,
updating the fault state of the ATPG machine to a fault state of the ATPG manager, the fault state of the ATPG manager representative of faults detected by the ATPG machine and the one or more other ATPG machines.
Regarding independent claim 1, independent claim 1 of U.S. Patent No. US 12,320,839 B2 meets all claim limitation of claim 1 except that the receiving information relating to the undetected faults and determined based at least on the information relating to the undetected faults.
JP 3621384 B2 teaches receiving information relating to undetected (e.g. fig. 2, S204 to S206, [0049], undetected failure information are received and stored), a faut state determined based on information relating to undetected faults (e.g. fig. 2, S204 to S206, [0049], detected / undetected status is determined as failure information is transmitted).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified claim 1 of U.S. Patent No. US 12,320,839 B2 by applying the teaching of JP 3621384 B2 to include the limitations of the receiving information relating to the undetected faults and determined based at least on the information relating to the undetected faults, for the purpose of increasing fault coverage by detecting additional undetected failures.
Regarding claims 2-7, claims 2-7 are met by claims 2-7 of U.S. Patent No. US 12,320,839 B2.
A comparison of the claims is presented in the following table with exact correspondence in bold face.
Instant Application
U.S. Patent No. US 12,320,839 B2
14. A non-transitory computer-readable apparatus comprising a storage medium,
the storage medium comprising a plurality of instructions configured to, when executed by one or more processors, cause the one or more processors to:
generate a first plurality of test patterns over a first interval;
communicate one or more faults associated with the first plurality of test patterns to an automatic test-pattern generation (ATPG) manager apparatus;
receive, from the ATPG manager, information indicative of faults detected by one or more other ATPG apparatus during the first interval; and
update a fault state of the ATPG manager apparatus with the information indicative of faults.
14. A non-transitory computer-readable apparatus comprising a storage medium,
the storage medium comprising a plurality of instructions configured to, when executed by one or more processors, cause the one or more processors to:
generate a first plurality of test patterns over a first interval;
responsive to the first plurality of test patterns meeting or exceeding a threshold quantity of test patterns,
identify one or more faults associated with the first plurality of test patterns;
communicate the identified one or more faults to an automatic test-pattern generation (ATPG) manager apparatus that is configured to communicate with one or more other ATPG apparatus; and
receive information indicative of faults detected by the one or more other ATPG apparatus during the first interval.
Regarding independent claim 14, independent claim 14 of U.S. Patent No. US 12,320,839 B2 meets all claim limitation of claim 14 except the claim limitation of “update a fault state of the ATPG manager apparatus with the information indicative of faults”.
JP 3621384 B2 teaches update a fault state with the information indicative of faults (e.g. [0031], failure information is updated based on the received failure information).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified claim 1 of U.S. Patent No. US 12,320,839 B2 by applying the teaching of JP 3621384 B2 to include the limitations of update a fault state of the ATPG manager apparatus with the information indicative of faults, for the purpose of keeping status of failure state information current and/or making the failure state information more accurate by having an up-to-date fault information.
Regarding claims 15-20, claims 15-20 are met by claims 15-20 of U.S. Patent No. US 12,320,839 B2.
Claims 8-13 are rejected on the ground of nonstatutory double patenting as being unpatentable over corresponding claims 8-13 of U.S. Patent No. US 12,320,839 B2
A comparison of the claims is presented in the following table with exact correspondence in bold face.
Instant Application
U.S. Patent No. US 12,320,839 B2
8. A system for automatic test-pattern generation (ATPG), the system
comprising:
one or more memory components; and
one or more processors coupled to the one or more memory components, the one or more processors configured to:
instruct a plurality of ATPG workers to generate a first set of test patterns; and
responsive to receiving, from the one or more ATPG workers, fault detections
associated with the first set of test patterns generated,
communicate to the plurality of ATPG workers the one or more fault detections previously undetected by the one or more ATPG workers.
8. A system for automatic test-pattern generation (ATPG), the system comprising:
one or more memory components;
one or more processors coupled to the one or more memory components, the one or more processors configured to:
instruct a plurality of ATPG workers to generate a first set of test patterns and
detect faults associated with the first set of test patterns;
receive fault detections from one or more of the plurality of ATPG workers; based on the fault detections from the one or more ATPG workers,
identify one or more fault detections previously undetected by the one or more ATPG workers; and
during a synchronization period triggered based on a prescribed criterion, communicate to the plurality of ATPG workers the one or more fault detections previously undetected by the one or more ATPG workers.
Regarding independent claim 8, independent claim 8 is met by independent claim 8 of U.S. Patent No. US 12,320,839 B2.
Regarding claims 9-13, claims 9-13 are met by claims 9-13 of U.S. Patent No. US 12,320,839 B2.
This is a double patenting rejection since the conflicting claims have been patented.
Prior Art of Record
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Goel et al. (US 2015/0347664) teaches a system for automatic test-pattern generation (ATPG) (e.g. fig. 8, [0074] and [0077], control system 800 having ATPG 816), the system comprising:
one or more memory components (e.g. fig. 8, [0077], memory 804); and
one or more processors coupled to the one or more memory components (e.g. fig. 8, processor 802), the one or
more processors configured to:
generate a first set of test patterns (e.g. fig. 8, [0081], generate ATPG 816).
Allowable Subject Matter
Claims 1-20 are objected to as being dependent upon nonstatutory double patenting rejection, but would be allowable if the nonstatutory double patenting of claims 1-20 are properly overcome without broadening the scopes of claims 1-20.
Reasons for Allowance
The following is an examiner’s statement of reasons for allowance:
Regarding independent claim 1, the cited and/or searched prior arts either singularly or in combination fail to teaches all the limitations of independent claim 1, in particular the claim limitation of “responsive to a degree of staleness of a fault state of the ATPG machine determined based at least on the information relating to the undetected faults, updating the fault state of the ATPG machine”; therefore, independent claim 1 is allowed, as are its dependent claims 2-7.
Regarding independent claim 8, the cited and/or searched prior arts either singularly or in combination fail to teaches all the limitations of independent claim 8, in particular the claim limitation of “responsive to receiving, from the one or more ATPG workers, fault detections associated with the first set of test patterns generated, communicate to the plurality of ATPG workers the one or more fault detections previously undetected by the one or more ATPG workers”; therefore, independent claim 8 is allowed, as are its dependent claims 9-13.
Regarding independent claim 14, the cited and/or searched prior arts either singularly or in combination fail to teaches all the limitations of independent claim 14, in particular the claim limitation of “receive, from the ATPG manager, information indicative of faults detected by one or more other ATPG apparatus during the first interval; and update a fault state of the ATPG manager apparatus with the information indicative of faults”; therefore, independent claim 14 is allowed, as are its dependent claims 15-20.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HAIDONG ZHANG whose telephone number is (571)270-5815. The examiner can normally be reached on M-F 8:00 AM - 5:00 PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Huy Phan can be reached on (571) 272-7924. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/HAIDONG ZHANG/Examiner, Art Unit 2858
/RAUL J RIOS RUSSO/ Examiner, Art Unit 2858
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