DETAILED ACTION
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 4/16/26 has been entered.
Response to Arguments
Regarding claim 1, it is argued that Mongia teaches the thermal conductivity layer is between a plurality of dies and not the now claimed every two adjacent dies.
Note that Mongia (beginning of paragraph 0092) states the set 102 comprises “one or more IC dies 104” and “set 102 may contain a single one of IC die 104.” Therefore the Mongia teaches the new claim limitation - a thermal conductivity layer is between a plurality of dies and not the now claimed every two adjacent dies.
With respect to claim 4, Applicant’s arguments, see the new claim limitation, have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made below.
As to claim 13, Applicant’s arguments, see the new claim limitations, have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made below.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claim(s) 1-3, and 5-12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tao et al., US 20180040587, in view of Applicant’s Admitted Prior Art (AAPA), in view of Mongia et al., US 2025/0140741.
Regarding claim 1, Tao (figures 13 & 17) teaches an IC structure comprising:
a memory stack comprising:
a plurality of semiconductor dies 106 horizontally separate with each other, wherein each semiconductor die 106 comprises a primary redistribution layer (RDL) 902, a top surface, a bottom surface opposite to the top surface, and four sidewalls with a first sidewall, a second sidewall, a third sidewall and a fourth sidewall, and a plurality of first edge pads 904 arranged along the first sidewall and exposed from the primary RDL 902, wherein the area of the bottom surface or the top surface of each semiconductor die 106 is larger than that of any sidewall;
a memory controlling chip 1502 under and electrically connected (through 102) to the plurality of first edge pads 904 of each semiconductor die 106, wherein the first sidewall of each semiconductor die 106 faces the memory controlling chip 1502, and power and/or data signals of each semiconductor die 106 are propagated to the memory controlling chip 1502 without through other semiconductor dies 106.
Tao fails to teach an interposer under and electrically connected to the memory controller controlling chip; a logic processor chip electrically connected to the memory controller controlling chip; and a packaging substrate under and electrically connected to the interposer.
AAPA teaches an interposer 23 under and electrically connected to the memory controlling chip 212; a logic processor chip 22 electrically connected to the memory controlling chip 212; and a packaging substrate 24 under and electrically connected to the interposer 23.
It would have been obvious to one of ordinary skill in the art at the time of the invention to use the configuration of AAPA in the invention of Tao because AAPA teaches a conventionally known and used package. The use of conventional materials to perform their known functions is obvious (MPEP 2144.07).
Tao fails to teach a plurality of upward extending thermal conductivity layers, wherein a corresponding upward extending thermal conductivity layer is disposed between every two adjacent semiconductor dies, wherein the thermal conductivity of the plurality of upward extending thermal conductivity layers is higher than that of Si or SiO2.
Mongia teaches a plurality of upward extending thermal conductivity layers 110, wherein a corresponding upward extending thermal conductivity layer 110 is disposed between every two adjacent semiconductor dies 104 (beginning of paragraph 0092 states the set 102 comprises “one or more IC dies 104” and “set 102 may contain a single one of IC die 104”), wherein the thermal conductivity of the plurality of upward extending thermal conductivity layers 110 is higher than that of Si or SiO2 (paragraph 0100 teaches 302=Cu & paragraph 0092 teaches 110=SiC & diamond).
It would have been obvious to one of ordinary skill in the art at the time of the invention to use the configuration of Mongia in the invention of Tao because Mongia teaches it improves thermal dissipation (paragraph 0030-0034).
With respect to claim 2, Mongia (figures 1A-1B &/or 3) teaches the memory stack further comprising: a laterally extending thermal conductivity layer 302 covering each second sidewall of the plurality of semiconductor dies 102 (wherein the set of dies 102 can contain one or more die 1043 (paragraph 0092), wherein the thermal conductivity of the laterally extending thermal conductivity layer 302 or the upward extending thermal conductivity layer is higher than that of Si or SiO2 (paragraph 0100 teaches 302=Cu & middle of paragraph 0092 teaches 110=SiC & diamond).
In re claim 3, Mongia (figure 3) teaches the upward extending thermal conductivity layer 110 is thermally coupling to the laterally extending thermal conductivity layer 302, and the upward extending thermal conductivity layer 110 or the laterally extending thermal conductivity layer 302 comprises SiC, BN, AlN, W, or copper (paragraph 0100 teaches 302-Cu).
With respect to claim 5, though Tao fails to teach each semiconductor die is a DRAM die and includes data output between 128~2048 bits, it would have been obvious to one ordinary skill in the art at the time of the invention to optimize the data output through routine experimentation (MPEP 2144.05).
As to claim 6, Tao (figure 13) teaches an edge redistribution layer (RDL) 902 having a first interconnect surface and a second interconnect surface opposite to the first interconnect surface, wherein the first interconnect surface covers the plurality of first edge pads 904 of each semiconductor die 106, and though Tao fails to teach the plurality of first edge pads 904 are electrically connected to a plurality of second edge pads at the second interconnect surface it would have been obvious to one of ordinary skill in the art at the time of the invention to use a plurality of second edge pads in the invention of Tao because they are conventionally known and used in the art. The use of conventional materials to perform their known functions is obvious (MPEP 2144.07).
In re claim 7, though Tao fails teach each first edge pad 904 includes a conductive via electrically connected to a signal pad (paragraph 0046) in a back-end-of-line (BEOL) region of each of the semiconductor dies 106 surrounded by a seal ring structure, it would have been obvious to one of ordinary skill in the art at the time of the invention to use this configuration in the invention of Tao because it is conventionally known and used in the art. The use of conventional materials to perform their known functions is obvious (MPEP 2144.07).
Concerning claim 8, though Tao fails teach each first edge pad of each semiconductor die includes a conductive line in the primary RDL, the conductive line electrically connected to a signal pad in a back-end-of-line (BEOL) region of the semiconductor die surrounded by a seal ring structure, it would have been obvious to one of ordinary skill in the art at the time of the invention to use this configuration in the invention of Tao because it is conventionally known and used in the art. The use of conventional materials to perform their known functions is obvious (MPEP 2144.07).
Pertaining to claim 9, though Tao fails to specifically teach the primary RDL includes a plurality of stacked dielectric layers within which the conductive line is located, it would have been obvious to one of ordinary skill in the art at the time of the invention to use this configuration in the invention of Tao because it is conventionally known and used in the art. The use of conventional materials to perform their known functions is obvious (MPEP 2144.07).
In claim 10, though Tao fails to specifically teach a portion of the conductive line is configured to be disposed in a scribe line region (SL) of a semiconductor wafer prior to dicing of the semiconductor wafer, it would have been obvious to one of ordinary skill in the art at the time of the invention to use this configuration in the invention of Tao because it is conventionally known and used in the art. The use of conventional materials to perform their known functions is obvious (MPEP 2144.07).
Regarding claim 11, AAPA teaches the logic processor chip 22 is disposed over the interposer 23, and though AAPA fails to teach a heat sink is over the logic processor chip; wherein a top surface of the heat sink is substantially leveled up with that of the memory stack, it would have been obvious to one of ordinary skill in the art at the time of the invention to use a heat sink in the invention of Mongia because a heat sink is conventionally known and used in the prior art. It would be substantially level because AAPA (figure 1) teaches the logic die 22 is level with the memory stack 21. The use of conventional materials to perform their known functions is obvious (MPEP 2144.07).
With respect to claim 12. (Original) The IC structure of claim 1, wherein the memory stack further comprises an upward extending thermal conductivity layer covering each third sidewall of the plurality of semiconductor dies; wherein the upward extending thermal conductivity layer is thermally coupling to a laterally extending thermal conductivity layer over each second sidewall of the plurality of semiconductor dies, and the thermal conductivity of the upward extending thermal conductivity layer is higher than that of Si or SiO2.
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tao et al., US 20180040587, in view of Applicant’s Admitted Prior Art (AAPA), in view of Mongia et al., US 2025/0140741, as applied to claim 1 above, and further in view of Bae et al., US 2023/0042063.
Concerning claim 4, Mongia fails to teach another upward extending thermal conductivity layer of the plurality of upward extending thermal conductivity layers is further disposed at a most lateral sidewall of the memory stack.
Bae (figure 1B) teaches another upward extending thermal conductivity layer (right most HP) of the plurality of upward extending thermal conductivity layers (other HP’s) is further disposed at a most lateral sidewall of the memory stack.
It would have been obvious to one of ordinary skill in the art at the time of the invention to use the configuration of Bae in the invention of Tao and Mongia because a skilled artisan knows that it would help improve heat dissipation from the device to the atmosphere.
Claim(s) 13-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tao et al., US 20180040587, in view of Applicant’s Admitted Prior Art (AAPA), and Kawano, US 2025/0286031.
Pertaining to claim 13, Tao (figures 3, 13 & 17) teaches an IC structure comprising:
a memory stack comprising:
a plurality of semiconductor dies 106 horizontally separate with each other, wherein each semiconductor die 106 comprises a primary redistribution layer (RDL) 902, a top surface, a bottom surface opposite to the top surface, and four sidewalls with a first sidewall, a second sidewall, a third sidewall and a fourth sidewall, and a plurality of edge pads 904 arranged along the first sidewall, wherein the area of the bottom surface or the top surface of each semiconductor die 106 is larger than that of any sidewall, wherein each of the plurality of edge pads 904 is revealed from an edge surface of the primary RDL 902;
wherein there is no through silicon via (TSV) in each semiconductor die 106;
a logic controlling chip 1502 under and electrically connected to the plurality of edge pads 904 (through 102), wherein the first sidewall of each semiconductor die 106 faces the logic controlling chip 1502.
Tao fails to teach the plurality of edge pads are extended outside a peripheral region defined by a seal ring structure of the semiconductor die, and wherein one of the plurality of edge pads of the semiconductor die includes a conductive line within the primary RDL and electrically connected to a corresponding signal pad within a back-end- of-line (BEOL) region of the semiconductor die by positioning above and spanning across the seal ring structure of the semiconductor die.
Kawano (figures 9B, 11A & 11B) teaches the plurality of edge pads 166 (figure 9B)/166a (figure 11B) are extended outside a peripheral region defined by a seal ring structure 160 of the semiconductor die, and wherein one of the plurality of edge pads 166 (figure 9B)/166a (figure 11B) of the semiconductor die includes a conductive line 166 (figures 9B, 11A & 11B)/ 165 (figure 3) within the primary RDL (figure 3:165/180/178) and electrically connected to a corresponding signal pad (paragraph 0181 states 166 it is a signal transmission wire therefore it attaches to a signal pad) within a back-end- of-line (BEOL) region of the semiconductor die by positioning above and spanning across the seal ring structure 160 of the semiconductor die.
It would have been obvious to one of ordinary skill in the art at the time of the invention to use a seal ring structure in the invention of Tao because Kawano (paragraph 0185) teaches a seal ring structure suppresses moisture absorption, impurities, corrosion, and deterioration. The use of conventional materials to perform their known functions is obvious (MPEP 2144.07).
Tao fails to teach an interposer under and electrically connected to the logic controlling chip; a logic processor chip electrically connected to the logic controlling chip; and a packaging substrate under and electrically connected to the interposer.
AAPA (figure 1) teaches an interposer 23 under and electrically connected to the logic controlling chip 212; a logic processor chip 22 electrically connected to the logic controlling chip 212 and a packaging substrate 24 under and electrically connected to the interposer 23.
It would have been obvious to one of ordinary skill in the art at the time of the invention to use the configuration of AAPA in the invention of Tao because AAPA teaches a conventionally known and used package. The use of conventional materials to perform their known functions is obvious (MPEP 2144.07).
In claim 14, though Tao fails to teach at least part of each edge pad 904 of the plurality of edge pads 904 of each semiconductor die 106 is disposed in a scribe line region of the semiconductor die 106, it would have been obvious to one of ordinary skill in the art at the time of the invention to use a scribe line region in the invention of Tao because a scribe line region is conventionally known and used in the art. The use of conventional materials to perform their known functions is obvious (MPEP 2144.07).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID A ZARNEKE whose telephone number is (571)272-1937. The examiner can normally be reached M-F.
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/DAVID A ZARNEKE/Primary Examiner, Art Unit 2891 5/19/26
Prosecution Insights