DETAILED ACTION
Response to Arguments
Regarding independent claim 1, it is argued that Mongia fails to teach the new limitation of thermal conductivity layers at the most lateral sidewall of the memory stack. And though Bae teaches thermal conductivity layers HP at the most lateral sidewall of the memory stack, they do not meet the new limitation of a top surface of each of the plurality of upward extending thermal conductivity layer is coplanar with each second sidewall of the plurality of semiconductor dies, the second sidewall being opposite to the first sidewall. Bae’s thermal conductivity layer are above the top of the sidewall.
Note that what is imported into Mongia from Bae is the concept of the thermal conductivity layer HP attached at the most lateral sidewall of the memory stack. When combining Bae’s thermal conductivity layer HP with Mongia, which teaches the thermal conductivity layer 110 is level with the most lateral sidewall of the memory stack, one must consider how it would apply to the teachings of Mongia. Bae’s thermal conductivity layer HP is not required to be bodily incorporated into Mongia. The concept of a thermal conductivity layer on the most lateral sidewall of the memory stack is what a skilled artisan would consider and then adapt to their specific configuration. In response to applicant's argument that Bae’s thermal conductivity layer does not meet the claim limitation, the test for obviousness is not whether the features of a secondary reference may be bodily incorporated into the structure of the primary reference; nor is it that the claimed invention must be expressly suggested in any one or all of the references. Rather, the test is what the combined teachings of the references would have suggested to those of ordinary skill in the art. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981).
Regarding independent claim 13, it is argued that Kawano does not teach an RDL layer on the die. What is alleged to be the RDL layer is actually a BEOL layer.
Note that Kawano states the transistor is region 130, and region 130 includes a BEOL layer (177/178/via under 178). The layer 150 is called a wiring layer that is a layer that redistributes the transistor pad 178 to the edge (at 165a). Therefore it is a RDL.
Lastly it is argued that Kawano fails to teach a peripheral region defined by a seal ring structure, wherein each of the plurality of edge pads is revealed from an edge surface of the primary RDL and extended outside a peripheral region defined by a seal ring structure of the semiconductor die.
Note that Kawano (figures 11A/11B) clearly teaches, as stated in the previous office action, a peripheral region (paragraph 0182) defined by a seal ring structure 160, wherein each of the plurality of edge pads 166a is revealed from an edge surface of the primary RDL 150 and extended outside a peripheral region defined by a seal ring structure 160 of the semiconductor die 110.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claim(s) 1-3, 5-12, and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tao et al., US 20180040587, in view of Applicant’s Admitted Prior Art (AAPA), in view of Mongia et al., US 2025/0140741, and Bae et al., US 2023/0042063.
Regarding claim 1, Tao (figures 13 & 17) teaches an IC structure comprising:
a memory stack comprising:
a plurality of semiconductor dies 106 horizontally separate with each other, wherein each semiconductor die 106 comprises a primary redistribution layer (RDL) 902/904, a top surface, a bottom surface opposite to the top surface, and four sidewalls with a first sidewall, a second sidewall, a third sidewall and a fourth sidewall, and a plurality of first edge pads 904 arranged along the first sidewall and exposed from the primary RDL 902/904, wherein the area of the bottom surface or the top surface of each semiconductor die 106 is larger than that of any sidewall;
a memory controlling chip 1502 under and electrically connected (through 102) to the plurality of first edge pads 904 of each semiconductor die 106, wherein the first sidewall of each semiconductor die 106 faces the memory controlling chip 1502, and power and/or data signals of each semiconductor die 106 are propagated to the memory controlling chip 1502 without through other semiconductor dies 106.
Tao fails to teach an interposer under and electrically connected to the memory controller controlling chip; a logic processor chip electrically connected to the memory controller controlling chip; and a packaging substrate under and electrically connected to the interposer.
AAPA teaches an interposer 23 under and electrically connected to the memory controlling chip 212; a logic processor chip 22 electrically connected to the memory controlling chip 212; and a packaging substrate 24 under and electrically connected to the interposer 23.
It would have been obvious to one of ordinary skill in the art at the time of the invention to use the configuration of AAPA in the invention of Tao because AAPA teaches a conventionally known and used package. The use of conventional materials to perform their known functions is obvious (MPEP 2144.07).
Tao fails to teach a plurality of upward extending thermal conductivity layers, wherein a corresponding upward extending thermal conductivity layer is disposed between every two adjacent semiconductor dies, wherein the thermal conductivity of the plurality of upward extending thermal conductivity layers is higher than that of Si or SiO2; and a laterally extending thermal conductivity layer covering each of the second sidewall of the plurality of semiconductor dies.
Mongia (figure 1) teaches a plurality of upward extending thermal conductivity layers 110, wherein a corresponding upward extending thermal conductivity layer 110 is disposed between every two adjacent semiconductor dies 104 (beginning of paragraph 0092 states the set 102 comprises “one or more IC dies 104” and “set 102 may contain a single one of IC die 104”), wherein the thermal conductivity of the plurality of upward extending thermal conductivity layers 110 is higher than that of Si or SiO2 (paragraph 0100 teaches 302=Cu & paragraph 0092 teaches 110=SiC & diamond); and Mongia (figure 3) teaches a laterally extending thermal conductivity layer 302 covering each of the second sidewall of the plurality of semiconductor dies 104.
It would have been obvious to one of ordinary skill in the art at the time of the invention to use the configuration of Mongia in the invention of Tao because Mongia teaches it improves thermal dissipation (paragraph 0030-0034).
Mongia fails to teach another upward extending thermal conductivity layer is disposed at a most lateral sidewall of the memory stack.
Bae fails to teach a top surface of each of the plurality of upward extending thermal conductivity layer is coplanar with each second sidewall of the plurality of semiconductor dies, the second sidewall being opposite to the first sidewall
Note that what is imported into Mongia from Bae is the concept of the thermal conductivity layer HP attached at the most lateral sidewall of the memory stack. When combining Bae’s thermal conductivity layer HP with Mongia, which teaches the thermal conductivity layer 110 is level with the most lateral sidewall of the memory stack, one must consider how it would apply to the teachings of Mongia. Bae’s thermal conductivity layer HP is not required to be bodily incorporated into Mongia. The concept of a thermal conductivity layer on the most lateral sidewall of the memory stack is what a skilled artisan would consider and then adapt to their specific configuration. In response to applicant's argument that Bae’s thermal conductivity layer does not meet the claim limitation, the test for obviousness is not whether the features of a secondary reference may be bodily incorporated into the structure of the primary reference; nor is it that the claimed invention must be expressly suggested in any one or all of the references. Rather, the test is what the combined teachings of the references would have suggested to those of ordinary skill in the art. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981).
With respect to claim 2, Mongia (figures 1A-1B &/or 3) teaches the thermal conductivity of the laterally extending thermal conductivity layer 302 or the upward extending thermal conductivity layer is higher than that of Si or SiO2 (paragraph 0100 teaches 302=Cu & middle of paragraph 0092 teaches 110=SiC & diamond).
In re claim 3, Mongia (figure 3) teaches the upward extending thermal conductivity layer 110 is thermally coupling to the laterally extending thermal conductivity layer 302, and the upward extending thermal conductivity layer 110 or the laterally extending thermal conductivity layer 302 comprises SiC, BN, AlN, W, or copper (paragraph 0100 teaches 302-Cu).
With respect to claim 5, though Tao fails to teach each semiconductor die is a DRAM die and includes data output between 128~2048 bits, it would have been obvious to one ordinary skill in the art at the time of the invention to optimize the data output through routine experimentation (MPEP 2144.05).
As to claim 6, Tao (figure 13) teaches an edge redistribution layer (RDL) 902 having a first interconnect surface and a second interconnect surface opposite to the first interconnect surface, wherein the first interconnect surface covers the plurality of first edge pads 904 of each semiconductor die 106, and though Tao fails to teach the plurality of first edge pads 904 are electrically connected to a plurality of second edge pads at the second interconnect surface it would have been obvious to one of ordinary skill in the art at the time of the invention to use a plurality of second edge pads in the invention of Tao because they are conventionally known and used in the art. The use of conventional materials to perform their known functions is obvious (MPEP 2144.07).
In re claim 7, though Tao fails teach each first edge pad 904 includes a conductive via electrically connected to a signal pad (paragraph 0046) in a back-end-of-line (BEOL) region of each of the semiconductor dies 106 surrounded by a seal ring structure, it would have been obvious to one of ordinary skill in the art at the time of the invention to use this configuration in the invention of Tao because it is conventionally known and used in the art. The use of conventional materials to perform their known functions is obvious (MPEP 2144.07).
Concerning claim 8, though Tao fails teach each first edge pad of each semiconductor die includes a conductive line in the primary RDL, the conductive line electrically connected to a signal pad in a back-end-of-line (BEOL) region of the semiconductor die surrounded by a seal ring structure, it would have been obvious to one of ordinary skill in the art at the time of the invention to use this configuration in the invention of Tao because it is conventionally known and used in the art. The use of conventional materials to perform their known functions is obvious (MPEP 2144.07).
Pertaining to claim 9, though Tao fails to specifically teach the primary RDL includes a plurality of stacked dielectric layers within which the conductive line is located, it would have been obvious to one of ordinary skill in the art at the time of the invention to use this configuration in the invention of Tao because it is conventionally known and used in the art. The use of conventional materials to perform their known functions is obvious (MPEP 2144.07).
In claim 10, though Tao fails to specifically teach a portion of the conductive line is configured to be disposed in a scribe line region (SL) of a semiconductor wafer prior to dicing of the semiconductor wafer, it would have been obvious to one of ordinary skill in the art at the time of the invention to use this configuration in the invention of Tao because it is conventionally known and used in the art. The use of conventional materials to perform their known functions is obvious (MPEP 2144.07).
Regarding claim 11, AAPA teaches the logic processor chip 22 is disposed over the interposer 23, and though AAPA fails to teach a heat sink is over the logic processor chip; wherein a top surface of the heat sink is substantially leveled up with that of the memory stack, it would have been obvious to one of ordinary skill in the art at the time of the invention to use a heat sink in the invention of Mongia because a heat sink is conventionally known and used in the prior art. It would be substantially level because AAPA (figure 1) teaches the logic die 22 is level with the memory stack 21. The use of conventional materials to perform their known functions is obvious (MPEP 2144.07).
With respect to claim 12, though Mongia and Bae fail to teach the memory stack further comprises an upward extending thermal conductivity layer covering each third sidewall of the plurality of semiconductor dies; wherein the upward extending thermal conductivity layer is thermally coupling to a laterally extending thermal conductivity layer over each second sidewall of the plurality of semiconductor dies, it would have been obvious to one of ordinary skill in the art at the time of the invention to use this configuration in the invention of Mongia and/or Bae because a skilled artisan knows it would further enhance thermal dissipation.
As to claim 15, Tao (figure 13) teaches a height of each primary RDL 902/9094 is identical to a height of each of the plurality of semiconductor dies 106.
Claim(s) 13-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tao et al., US 20180040587, in view of Applicant’s Admitted Prior Art (AAPA), and Kawano, US 2025/0286031.
Pertaining to claim 13, Tao (figures 3, 13 & 17) teaches an IC structure comprising:
a memory stack comprising:
a plurality of semiconductor dies 106 horizontally separate with each other, wherein each semiconductor die 106 comprises a primary redistribution layer (RDL) 902, a top surface, a bottom surface opposite to the top surface, and four sidewalls with a first sidewall, a second sidewall, a third sidewall and a fourth sidewall, and a plurality of edge pads 904 arranged along the first sidewall, wherein the area of the bottom surface or the top surface of each semiconductor die 106 is larger than that of any sidewall, wherein each of the plurality of edge pads 904 is revealed from an edge surface of the primary RDL 902;
wherein there is no through silicon via (TSV) in each semiconductor die 106;
a logic controlling chip 1502 under and electrically connected to the plurality of edge pads 904 (through 102), wherein the first sidewall of each semiconductor die 106 faces the logic controlling chip 1502.
Tao fails to teach the plurality of edge pads are extended outside a peripheral region defined by a seal ring structure of the semiconductor die, and wherein one of the plurality of edge pads of the semiconductor die includes a conductive line within the primary RDL and electrically connected to a corresponding signal pad within a back-end- of-line (BEOL) region of the semiconductor die by positioning above and spanning across the seal ring structure of the semiconductor die.
Kawano (figures 9B, 11A & 11B) teaches the plurality of edge pads 166 (figure 9B)/166a (figure 11B) are extended outside a peripheral region (paragraph 0182) defined by a seal ring structure 160 of the semiconductor die, and wherein one of the plurality of edge pads 166 (figure 9B)/166a (figure 11B) of the semiconductor die includes a conductive line 166 (figures 9B, 11A & 11B)/165 (figure 3) within the primary RDL (figure 3:150) and electrically connected to a corresponding signal pad (paragraph 0181 states 166 it is a signal transmission wire therefore it attaches to a signal pad) within a back-end- of-line (BEOL) region (177/178) of the semiconductor die by positioning above and spanning across the seal ring structure 160 of the semiconductor die.
It would have been obvious to one of ordinary skill in the art at the time of the invention to use a seal ring structure in the invention of Tao because Kawano (paragraph 0185) teaches a seal ring structure suppresses moisture absorption, impurities, corrosion, and deterioration. The use of conventional materials to perform their known functions is obvious (MPEP 2144.07).
Tao fails to teach an interposer under and electrically connected to the logic controlling chip; a logic processor chip electrically connected to the logic controlling chip; and a packaging substrate under and electrically connected to the interposer.
AAPA (figure 1) teaches an interposer 23 under and electrically connected to the logic controlling chip 212; a logic processor chip 22 electrically connected to the logic controlling chip 212 and a packaging substrate 24 under and electrically connected to the interposer 23.
It would have been obvious to one of ordinary skill in the art at the time of the invention to use the configuration of AAPA in the invention of Tao because AAPA teaches a conventionally known and used package. The use of conventional materials to perform their known functions is obvious (MPEP 2144.07).
In claim 14, though Tao fails to teach at least part of each edge pad 904 of the plurality of edge pads 904 of each semiconductor die 106 is disposed in a scribe line region of the semiconductor die 106, it would have been obvious to one of ordinary skill in the art at the time of the invention to use a scribe line region in the invention of Tao because a scribe line region is conventionally known and used in the art. The use of conventional materials to perform their known functions is obvious (MPEP 2144.07).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID A ZARNEKE whose telephone number is (571)272-1937. The examiner can normally be reached M-F.
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/DAVID A ZARNEKE/Primary Examiner, Art Unit 2891 9/4/26
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