DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 have been examined.
Priority
Applicant’s claim for the benefit of a prior-filed application under 35 U.S.C. 119(a)-(e) or under 35 U.S.C. 120, 121, 365(c), or 386(c) is acknowledged. The instant application claims priority to a chain of earlier applications, the earliest of which was filed May 8, 2017.
Information Disclosure Statement
The Applicant's submission of the Information Disclosure Statement dated September 4, 2025 is acknowledged by the Examiner. The cited references have been considered in the examination of the claims now pending, except as otherwise indicated. A number of NPL references were excluded because the Applicant did not comply with 37 CFR 1.98(d), which states, “A copy of any patent, publication, pending U.S. application or other information, as specified in paragraph (a) of this section, listed in an information disclosure statement is required to be provided, even if the patent, publication, pending U.S. application or other information was previously submitted to, or cited by, the Office in an earlier application, unless: (1) The earlier application is properly identified in the information disclosure statement…” In order to have the publications listed on the face of the patent, should the current application be allowed, the Applicant must either update the citations to identify which earlier application included the publications or submit the publications in this application. A copy of the PTOL-1449 initialed and dated by the Examiner is attached to the instant office action.
Drawings
The drawings are objected to because of the following informalities.
Figure 7 includes text that is improperly placed on a shaded surface. The figure therefore fails to comply with 37 CFR 1.84(p)(3), which states, “Numbers, letters, and reference characters … should not be placed upon hatched or shaded surfaces. When necessary, such as indicating a surface or cross section, a reference character may be underlined and a blank space may be left in the hatching or shading where the character occurs so that it appears distinct.”
In Figure 13, the reference characters 1301-1306 lack underlining and lead lines. One or the other is required. The figure therefore fails to comply with 37 CFR 1.84(q), which states, “Lead lines are required for each reference character except for those which indicate the surface or cross section on which they are placed. Such a reference character must be underlined to make it clear that a lead line has not been left out by mistake.”
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the Applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over corresponding claims of U.S. Patent No. 11,797,301 (Application No. 17/141,082). Although the claims at issue are not identical, they are not patentably distinct from each other because the claims in the reference patent anticipate those of the instant application.
Claims 1, 3-5, 7, 9-13, 15, 16, and 18-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over corresponding claims of U.S. Patent No. 11,797,303 (Application No. 17/351,175). Although the claims at issue are not identical, they are not patentably distinct from each other because the claims in the reference patent anticipate those of the instant application.
Claims 1, 3-5, 7, 9-13, 15, 16, and 18-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over corresponding claims of U.S. Patent No. 11,797,302 (Application No. 17/351,161). Although the claims at issue are not identical, they are not patentably distinct from each other because the claims in the reference patent anticipate those of the instant application.
Claims 1, 3-5, 7, 9-13, 15, 16, and 18-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over corresponding claims of U.S. Patent No. 12,321,743 (Application No. 18/377,718). Although the claims at issue are not identical, they are not patentably distinct from each other because the claims in the reference patent anticipate those of the instant application.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 2, 4-9, and 12-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US Publication No. 2018/0004510 by Grochowski et al. (hereinafter referred to as “Grochowski”).
Regarding claim 1, Grochowski discloses:
a multi-threaded processor, comprising: a decoder to decode a matrix multiply and accumulate (MMA) instruction (Grochowski discloses, at Figure 1 and related description, a processor that includes a decode unit to decode a matrix multiplication instruction. As disclosed at ¶ [0115], the processor can be multi-threaded. As disclosed at ¶ [0026], the instruction may be a matrix multiply and accumulate instruction.);
a buffer to store data specified by operands of the MMA instruction (Grochowski discloses, at ¶ [0054] caching, i.e., buffering, matrix data specified by the operands of the MMA instruction. This discloses a cache, i.e., buffer to do so.);
a scheduler to schedule the MMA instruction (Grochowski discloses, at Figure 9B and related description, a scheduler unit.);
a fused multiply accumulate (FMA) unit to perform operations using the data (Grochowski discloses, at Figure 5 and related description, fused matrix multiplication and addition logic.);
logic to process intermediate results generated based, at least in part, on the operations performed using the data (Grochowski discloses, at ¶ [0050], storing portions of result data to a destination, which discloses processing intermediate results based on the operations performed using the data.);
an arithmetic logic unit (ALU) to add the intermediate results to be accumulated into a register (Grochowski discloses, at ¶ [0050], accumulating, i.e., adding, the intermediate results. As disclosed at ¶ [0120], adding can be performed by an ALU. As disclosed at ¶ [0062], operands can be stored in registers.); and
memory to store a result of the MMA instruction (Grochowski discloses, at Figure 5 and related description, memory to store the destination, i.e., result, matrix.).
Regarding claim 2, Grochowski discloses the elements of claim 1, as discussed above. Grochowski also discloses:
the logic to process the intermediate results comprises logic to shift the intermediate results (Grochowski discloses, at ¶ [0111], the execution units include logic to shift various types of data, which is interpreted as including the intermediate data.).
Regarding claim 4, Grochowski discloses the elements of claim 1, as discussed above. Grochowski also discloses:
a dispatch unit to transmit the MMA instruction to the FMA unit (Grochowski discloses, at Figure 9A and related description, diapatching instructions. See, e.g., ¶ [0108].).
Regarding claim 5, Grochowski discloses the elements of claim 1, as discussed above. Grochowski also discloses:
a register file to provide the register, the register file configured to store the operands specified in the MMA instruction (Grochowski discloses, at Figure 9B and related description, register files.).
Regarding claim 6, Grochowski discloses the elements of claim 1, as discussed above. Grochowski also discloses:
the register has a width of 64-bits (Grochowski discloses, at ¶ [0062], 64-bit registers.).
Regarding claim 7, Grochowski discloses the elements of claim 1, as discussed above. Grochowski also discloses:
an interconnect to connect the ALU and the register, wherein the interconnect is to be used to accumulate the intermediate results into the register (Grochowski discloses, at ¶ [0050], accumulating, i.e., adding, the intermediate results. As disclosed at ¶ [0120], adding can be performed by an ALU. As disclosed at ¶ [0062], operands can be stored in registers, which discloses an interconnect to transfer the data.).
Regarding claim 8, Grochowski discloses the elements of claim 1, as discussed above. Grochowski also discloses:
a system memory to provide workloads to the multi-threaded processor, a workload of the workloads comprising a number of instructions and data to be processed by the number of instructions (Grochowski discloses, at Figure 5 and related description, storing data to be operated on in system memory. As disclosed at ¶ [0026], instructions can also be stored in system memory.); and
a system bus to connect the multi-threaded processor to the system memory (Grochowski discloses, at ¶ [0026], a bus to retrieve information from system memory.).
Regarding claim 9, Grochowski discloses:
a single instruction multiple data (SIMD) multi-threaded processor, comprising: a plurality of cores to perform a matrix multiply and accumulate (MMA) instruction, where each of the plurality of cores comprises (Grochowski discloses, at Figure 1 and related description, a processor to perform MMA instructions. As disclosed at ¶ [0104], the processor can include multiple cores and use SIMD. As disclosed at ¶ [0115], the processor can employ multithreading.):
a front end to fetch the MMA instruction (Grochowski discloses, at Figure 9B and related description, the processor can include a front end including a fetch unit.);
an instruction cache to store the MMA instruction (Grochowski discloses, at Figure 9B and related description, instruction cache.);
an L1 cache to store data (Grochowski discloses, at Figure 10A and related description, L1 cache to store data.);
an L2 cache to store data (Grochowski discloses, at Figure 10A and related description, L2 cache to store data.);
a plurality of ports to read from and write to a memory (Grochowski discloses, at ¶ [0033], ports to transfer data.);
one or more load/store units to read and write the memory (Grochowski discloses, at ¶ [0112], load and store units.);
an interconnect to couple the memory and the plurality of cores (Grochowski discloses, at Figure 9B and related description, the memory is coupled to the cores.);
a decoder to decode the MMA instruction (Grochowski discloses, at Figure 9B and related description, a decoder.);
a buffer to store data specified by operands of the MMA instruction (Grochowski discloses, at ¶ [0054] caching, i.e., buffering, matrix data specified by the operands of the MMA instruction. This discloses a cache, i.e., buffer to do so.);
a scheduler to schedule the MMA instruction (Grochowski discloses, at Figure 9B and related description, a scheduler unit.);
a fused multiply accumulate (FMA) unit to perform operations using the data specified by the operands of the MMA instruction (Grochowski discloses, at Figure 5 and related description, fused matrix multiplication and addition logic.);
logic to process intermediate results generated based, at least in part, on the operations performed using the data specified by the operands of the MMA instruction (Grochowski discloses, at ¶ [0050], storing portions of result data to a destination, which discloses processing intermediate results based on the operations performed using the data.); and
an arithmetic logic unit (ALU) to add the intermediate results to be accumulated into a register (Grochowski discloses, at ¶ [0050], accumulating, i.e., adding, the intermediate results. As disclosed at ¶ [0120], adding can be performed by an ALU. As disclosed at ¶ [0062], operands can be stored in registers.),
wherein the memory is to store a result of the MMA instruction (Grochowski discloses, at Figure 5 and related description, memory to store the destination, i.e., result, matrix.).
Regarding claim 12, Grochowski discloses the elements of claim 9, as discussed above. Grochowski also discloses:
the interconnect is to connect the one or more load/store units to the register (Grochowski discloses, at Figure 9B and related description, load store units are coupled to the register file, which discloses an interconnect.).
Regarding claim 13, Grochowski discloses the elements of claim 9, as discussed above. Grochowski also discloses:
the scheduler is to dispatch the MMA instruction to one or more cores of the plurality of cores (Grochowski discloses, at Figure 9A and related description, the scheduler dispatches instructions. See, e.g., ¶ [0108].).
Regarding claim 14, Grochowski discloses the elements of claim 9, as discussed above. Grochowski also discloses:
the logic to process the intermediate results comprises logic to shift the intermediate results (Grochowski discloses, at ¶ [0111], the execution units include logic to shift various types of data, which is interpreted as including the intermediate data.).
Regarding claim 15, Grochowski discloses:
a computer-implemented method, comprising: decoding, by a decoder, a matrix multiply and accumulate (MMA) instruction (Grochowski discloses, at Figure 1 and related description, a processor that includes a decode unit to decode a matrix multiplication instruction. As disclosed at ¶ [0115], the processor can be multi-threaded. As disclosed at ¶ [0026], the instruction may be a matrix multiply and accumulate instruction.);
storing, by a buffer, data specified by operands of the MMA instruction (Grochowski discloses, at ¶ [0054] caching, i.e., buffering, matrix data specified by the operands of the MMA instruction. This discloses a cache, i.e., buffer to do so.);
scheduling, by a scheduler, the MMA instruction (Grochowski discloses, at Figure 9B and related description, a scheduler unit.);
performing, by a fused multiply accumulate (FMA) unit, operations using the data (Grochowski discloses, at Figure 5 and related description, fused matrix multiplication and addition logic.);
processing, by logic to process, intermediate results generated based, at least in part, on the operations performed using the data (Grochowski discloses, at ¶ [0050], storing portions of result data to a destination, which discloses processing intermediate results based on the operations performed using the data.);
adding, by an arithmetic logic unit (ALU), the intermediate results to be accumulated into a register (Grochowski discloses, at ¶ [0050], accumulating, i.e., adding, the intermediate results. As disclosed at ¶ [0120], adding can be performed by an ALU. As disclosed at ¶ [0062], operands can be stored in registers.); and
storing, by a memory, a result of the MMA instruction (Grochowski discloses, at Figure 5 and related description, memory to store the destination, i.e., result, matrix.).
Regarding claim 16, Grochowski discloses the elements of claim 15, as discussed above. Grochowski also discloses:
the ALU comprises at least one adder (Grochowski discloses, at ¶ [0050], accumulating, i.e., adding, the intermediate results, which discloses at least one adder.).
Regarding claim 17, Grochowski discloses the elements of claim 15, as discussed above. Grochowski also discloses:
processing the intermediate results comprises shifting, by logic to shift, the intermediate results (Grochowski discloses, at ¶ [0111], the execution units include logic to shift various types of data, which is interpreted as including the intermediate data.).
Regarding claim 18, Grochowski discloses the elements of claim 15, as discussed above. Grochowski also discloses:
the scheduler comprises a dispatch unit to dispatch the MMA instruction (Grochowski discloses, at Figure 9A and related description, diapatching instructions. See, e.g., ¶ [0108].).
Regarding claim 19, Grochowski discloses the elements of claim 15, as discussed above. Grochowski also discloses:
accumulating the intermediate results into the register using an interconnect (Grochowski discloses, at ¶ [0050], accumulating, i.e., adding, the intermediate results. As disclosed at ¶ [0120], adding can be performed by an ALU. As disclosed at ¶ [0062], operands can be stored in registers, which discloses an interconnect to transfer the data.).
Regarding claim 20, Grochowski discloses the elements of claim 15, as discussed above. Grochowski also discloses:
a register file is to provide the register, the register file configured to store operands specified in the MMA instruction (Grochowski discloses, at Figure 9B and related description, register files.).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Grochowski in view of US Publication No. 2006/0101242 by Siu et al. (hereinafter referred to as “Siu”).
Regarding claim 3, Grochowski discloses the elements of claim 1, as discussed above. Grochowski does not explicitly disclose a tree of adders, where the tree of adders comprises at least a 3:2 carry sum adder (CSA).
However, in the same field of endeavor (e.g., arithmetic operations) Siu discloses:
a tree of adders, where the tree of adders comprises at least a 3:2 carry sum adder (CSA) (Siu discloses, at ¶ [0089], a tree of adders including 3:2 CSAs.).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Grochowski to include an adder tree including 3:2 CSAs because such an arrangement is a well-known mechanism to quickly and efficiently add numbers.
Claims 10 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Grochowski in view of Official Notice.
Regarding claim 10, Grochowski discloses the elements of claim 9, as discussed above. Grochowski does not explicitly disclose the L1 cache comprises at least 24 kilobytes (KB) of storage.
However, the Examiner takes Official notice that L1 cache having various sizes, including at least 24 KB, was notoriously well-known in the art prior to the effective filing date of the claimed invention. Including at least a given size allows sufficient storage for the particular operations for which the processor is intended.
Regarding claim 11, Grochowski discloses the elements of claim 9, as discussed above. Grochowski does not explicitly disclose the memory comprises at least 64 kilobytes (KB) of storage.
However, the Examiner takes Official notice that memory having various sizes, including at least 64 KB, was notoriously well-known in the art prior to the effective filing date of the claimed invention. Including at least a given size allows sufficient storage for the particular operations for which the processor is intended.
Conclusion
The following prior art made of record and not relied upon is considered pertinent to Applicant’s disclosure.
US 5918062 by Oberman discloses matrix multiply and intermediate values.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHAWN DOMAN whose telephone number is (571)270-5677. The examiner can normally be reached on Monday through Friday 8:30am-6pm Eastern Time.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jyoti Mehta can be reached on 571-270-3995. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SHAWN DOMAN/Primary Examiner, Art Unit 2183
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