DETAILED ACTION
This correspondence is in response to the communications received 06/09/2025. Claims 1-7 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 02/24/2026 and 05/19/2026 have been considered by the examiner and made of record in the application file.
Double Patenting
Claims 1, 2, and 4 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-3 of U.S. Patent No. 12,690,426, hereinafter ‘426, in view of Sills et al. (US 8,021,897 B2), in view of LiCausi (US 10,677,855 B2). See analysis below.
Regarding claim 1:
Instant Claim Limitation
Reference Limitation
A semiconductor testing structure
“A semiconductor testing structure” (‘426, claim 1)
a substrate
“a substrate” (‘426, claim 1)
a first metal layer disposed on the substrate and comprising a plurality of fingers extending along a first direction
“a first metal layer comprising a plurality of fingers extending along a first direction” (‘426, claim 1)
‘426 does not specifically disclose “a first metal layer disposed on the substrate”.
However, in a similar field of endeavor, Figs. 1-11 of Sill teaches a first metal layer (“first electrode material 14”, col. 2, line 53) disposed on the substrate (“base 12”, col. 2, line 36, “If the base comprise a semiconductor material, base 12 may be referred to as a semiconductor substrate”, col. 2, lines 36-38, and as seen in Fig. 11 of Sills, 14 is on 12).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “a first metal layer disposed on the substrate” as taught by Sills in the system of ‘426 for the purpose of supporting and protecting the first metal layer.
a dielectric structure disposed on the first metal layer
“a dielectric structure disposed on the first metal layer” (‘426, claim 1)
a second metal layer disposed on the dielectric structure and electrically isolated from the first metal layer, wherein the second metal layer extends along a second direction different from the first direction
“a plurality of second metal layers extending along a second direction different from the first direction” (‘426, claim 1)
‘426 does not specifically disclose “a second metal layer disposed on the dielectric structure and electrically isolated from the first metal layer”.
However, in a similar field of endeavor, Fig. 1 of LiCausi teaches a second metal layer disposed on the dielectric structure and electrically isolated from the first metal layer (“a given electrical ground element 120 can be under a given sub-array 110. Whether electrical ground element 120 is under all sub-arrays 110 or only under a given sub-array 110, electrical ground element 120 is electrically isolated from the sub-arrays by, for example, a dielectric layer”, col. 4, lines 1-6, where 120 is a first metal layer and 110 is a second metal layer)
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “a second metal layer disposed on the dielectric structure and electrically isolated from the first metal layer” as taught by LiCausi in the system of ‘426 for the purpose of preventing the two metal layers from shorting and thus enabling testing of the intervening dielectric structure.
a plurality of second metal layers, a first portion of the second metal layers has a first pitch, and a second portion of the second metal layers has a second pitch different from the first pitch
“a first portion of the second metal layer has a first pitch, and a second portion of the second metal layer has a second pitch different from the first pitch” (‘426, claim 2)
a plurality of second metal layers, and each of the plurality of second metal layers has a first terminal electrically connected to a first conductive pad and a second terminal electrically connected to a second conductive pad
‘426 does not specifically disclose “a plurality of second metal layers, and each of the plurality of second metal layers has a first terminal electrically connected to a first conductive pad and a second terminal electrically connected to a second conductive pad”.
However, in a similar field of endeavor, LiCausi teaches a plurality of second metal layers (“sub-array 410a, 410b, 410c, 410d, 410e”, col. 5, lines 37-38), and each of the plurality of second metal layers has a first terminal electrically connected to a first conductive pad and a second terminal electrically connected to a second conductive pad (“each sub-array 410a, 410b, 410c, 410d, 410e is connected to two bond pads, namely A1/A2, B1/B2, C1/C2, D1/D2 and E1/E2 respectively”, col. 5, lines 37-39, where 410a-410e are a plurality of second metal layers that are each connected to first and second conductive pads with first and second terminals at the junctions between the sub-arrays and respective conductive pads).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “a plurality of second metal layers, and each of the plurality of second metal layers has a first terminal electrically connected to a first conductive pad and a second terminal electrically connected to a second conductive pad” as taught by LiCausi in the system of ‘426 for the purpose of providing additional connectivity to the plurality of second metal layers.
Regarding claim 2:
Instant Claim Limitation
Reference Limitation
a conductive layer disposed on a lateral surface of the second metal layer
“a plurality of conductive layers… wherein each of the conductive layers disposed on a lateral surface and an upper surface of each of the plurality of second metal layers” (‘426, claim 1)
Regarding claim 4:
Instant Claim Limitation
Reference Limitation
wherein the dielectric structure comprises a first dielectric layer and a second dielectric layer over the first dielectric layer
“wherein the dielectric structure comprises a first dielectric layer and a second dielectric layer over the first dielectric layer” (‘426, claim 1)
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Objections
Claim objected to because of the following informalities: Claim . It appears this limitation should be written as “a plurality of second metal layers, a first portion of … [[a]] the plurality of second metal layers, and each of the …” Appropriate correction is required.
Claim 7 is objected to because of the following informalities: Claim 7 requires "wherein the lateral surface of the first dielectric layer is not coplanar with a lateral surface of the second metal layer, and the lateral surface of the second dielectric layer is not coplanar with a lateral surface of the second metal layer". It appears this limitation should be written as “wherein the lateral surface of the first dielectric layer is not coplanar with a lateral surface of the second metal layer, and the lateral surface of the second dielectric layer is not coplanar with [[a]] the lateral surface of the second metal layer” Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 3 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 3 recites the limitation “the conductive layer” in line 2. There is insufficient antecedent basis for this limitation in the claim.
Applicant’s Claim to Figure Comparison
It is noted that this comparison is merely for the benefit of reviewers of this office action during prosecution, to allow for an understanding of the examiner’s interpretation of the Applicant’s independent claims as compared to disclosed embodiments in Applicant’s Figures. No response or comments are necessary from Applicant.
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Regarding claim 1, A semiconductor testing structure (100a), comprising:
a substrate (110);
a first metal layer (140) disposed on the substrate and comprising a plurality of fingers (141) extending along a first direction (X, see Figs. 3 and 4B);
a dielectric structure (150) disposed on the first metal layer (see Fig. 4A);
a second metal layer (160) disposed on the dielectric structure and electrically isolated from the first metal layer (see Figs. 4A and 4B) , wherein the second metal layer extends along a second direction (Y) different from the first direction (see Fig. 4B);
a plurality of second metal layers, a first portion (161) of the second metal layers has a first pitch (T1), and a second portion (162) of the second metal layers has a second pitch (T2) different from the first pitch (see Fig. 3); and
a plurality of second metal layers, and each of the plurality of second metal layers has a first terminal (160t1) electrically connected to a first conductive pad (173) and a second terminal (160t2) electrically connected to a second conductive pad (174).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 1 is rejected under 35 U.S.C. 103 as being unpatentable over Sills et al. (US 8,021,897 B2, published 09/20/2011) in view of LiCausi (US 10,677,855 B2, published 06/09/2020).
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Regarding claim 1, Figs. 1-11 of Sills discloses a semiconductor testing structure (Sills does not specifically disclose a semiconductor testing structure, however the device structure disclosed by Sills does not appear to substantially differ from that disclosed in the instant application), comprising:
a substrate (“base 12”, col. 2, line 36, “If the base comprise a semiconductor material, base 12 may be referred to as a semiconductor substrate”, col. 2, lines 36-38);
a first metal layer (“first electrode material 14”, col. 2, line 53) disposed on the substrate (as seen in Fig. 2, 14 is on 12) and comprising a plurality of fingers extending along a first direction (as seen in Fig. 2, 14 has a plurality of fingers extending forwards and backwards);
a dielectric structure (together “first insulative material 18”, col. 2, line 61, and “second insulative material 20”, col. 2, line 62, form a dielectric structure) disposed on the first metal layer (as seen in Fig. 11, 18 and 20 are on 14);
a second metal layer (“top electrode material 46”, col. 5, line 1, where each instance of 46 represents an individual second metal layer) disposed on the dielectric structure (as seen in Fig. 11, 46 is disposed on 18 and 20) and electrically isolated from the first metal layer (as seen in Fig. 11, 46 is separated from 14 by 18 and 20 as well as “dielectric material 34”, col. 4, line 24, thus as dielectric materials are known in the art as electrically insulating, 46 is electrically isolated from 14), wherein the second metal layer extends along a second direction different from the first direction (as seen in Fig. 11, 46 extends from left to right of the device, orthogonal to 14);
a plurality of second metal layers (together all the instances of 46 forma plurality of second metal layers),
Sills fails to disclose “a first portion of the second metal layers has a first pitch, and a second portion of the second metal layers has a second pitch different from the first pitch; and
a plurality of second metal layers, and each of the plurality of second metal layers has a first terminal electrically connected to a first conductive pad and a second terminal electrically connected to a second conductive pad.”
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However, in a similar field of endeavor, Fig. 4 of LiCausi teaches a first portion of the second metal layers has a first pitch, and a second portion of the second metal layers has a second pitch different from the first pitch (as seen in Fig. 4, “metal wires 410a, 410b”, col. 5, line 32, have different pitches where 410a is a first portion of a second metal layer equivalent to a first instance of 46 of Sills, and 410b is a second portion of a second metal layer equivalent to a second instance of 46 of Sills); and
a plurality of second metal layers, and each of the plurality of second metal layers has a first terminal electrically connected to a first conductive pad and a second terminal electrically connected to a second conductive pad (as seen in Fig. 4, “each sub-array 410a, 410b, 410c, 410d, 410e is connected to two bond pads, namely A1/A2, B1/B2, C1/C2, D1/D2 and E1/E2 respectively”, col. 5, lines 37-39, where the two ends of 410a-410e each form a pair of terminals electrically connected to respective bond pads).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “a first portion of the second metal layers has a first pitch, and a second portion of the second metal layers has a second pitch different from the first pitch; and
a plurality of second metal layers, and each of the plurality of second metal layers has a first terminal electrically connected to a first conductive pad and a second terminal electrically connected to a second conductive pad” as taught by LiCausi in the system of Sills for the purpose of testing multiple device spacings in one structure.
Claims 2-4, 6, and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Sills et al. (US 8,021,897 B2, published 09/20/2011) in view of LiCausi (US 10,677,855 B2, published 06/09/2020) in view of Kato et al. (US 9,431,412 B1, published 08/30/2016).
Regarding claim 2, Figs. 1-11 of Sills in combination with Fig. 4 of LiCausi disclose the semiconductor testing structure of claim 1.
Sills in combination with LiCausi fails to disclose “further comprising:
a conductive layer disposed on a lateral surface of the second metal layer.”
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However, in a similar field of endeavor, Figs. 1-3 of Kato disclose further comprising:
a conductive layer (“barrier metal film 23”, col. 6, line 39) disposed on a lateral surface of the second metal layer (as seen in Fig. 2, 23 is disposed on a lateral surface of “electrically conductive member 24”, col. 6, lines 28-39, where “barrier metal film 23 is a film for preventing the electrically conductive material of the electrically conductive member 24 from spreading”, col. 6, lines 50-53, and 24 of Kato is equivalent to 46 of Sills).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “further comprising:
a conductive layer disposed on a lateral surface of the second metal layer” as taught by Kato in the system of Sills in combination with LiCausi for the purpose of preventing atomic diffusion of the second metal layer.
Regarding claim 3, Figs. 1-11 of Sills in combination with Fig. 4 of LiCausi disclose the semiconductor testing structure of claim 1.
Sills in combination with LiCausi fails to disclose “wherein the conductive layer is disposed on a sidewall of the dielectric structure”.
However, in a similar field of endeavor, Figs. 1-3 of Kato disclose wherein the conductive layer (“barrier metal film 23”, col. 6, line 39, and as seen in Fig. 2, 23 is disposed on “electrically conductive member 24”, col. 6, lines 28-39, where “barrier metal film 23 is a film for preventing the electrically conductive material of the electrically conductive member 24 from spreading”, col. 6, lines 50-53, and 24 of Kato is equivalent to 46 of Sills) is disposed on a sidewall of the dielectric structure (after combination with Sills, 23 of Kato will be disposed on 46 of Sills, thus 23 of Kato will be above and therefore on the sidewalls of 18 and 20 of Sills).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “wherein the conductive layer is disposed on a sidewall of the dielectric structure” as taught by Kato in the system of Sills in combination with LiCausi for the purpose of preventing atomic diffusion of the second metal layer.
Figs. 1-11 of Sills further disclose the sidewall extends between the first metal layer and the second metal layer (as seen in Fig. 11, the sidewalls of 18 and 20 extend between 14 and 46).
Regarding claim 4, Figs. 1-11 of Sills in combination with Fig. 4 of LiCausi and Figs. 1-3 of Kato disclose the semiconductor testing structure of claim 2, Figs. 1-11 of Sills further disclose wherein the dielectric structure comprises a first dielectric layer (18 is a first dielectric layer) and a second dielectric layer (20 is a second dielectric layer) over the first dielectric layer (as seen in Fig. 11, 20 is over 18).
Regarding claim 6, Figs. 1-11 of Sills in combination with Fig. 4 of LiCausi and Figs. 1-3 of Kato disclose the semiconductor testing structure of claim 4, Figs. 1-11 of Sills further disclose wherein a lateral surface of the first dielectric layer is substantially coplanar with a lateral surface of the second dielectric layer (as seen in Fig. 11, the upper surface of 18 which is a lateral surface is substantially coplanar with the lower surface of 20 which is also a lateral surface).
Regarding claim 7, Figs. 1-11 of Sills in combination with Fig. 4 of LiCausi and Figs. 1-3 of Kato disclose the semiconductor testing structure of claim 6, Figs. 1-11 of Sills further disclose wherein the lateral surface of the first dielectric layer is not coplanar with a lateral surface of the second metal layer (as seen in Fig. 11, the upper surface of 18 is not coplanar with a lower surface of 46 which is a lateral surface), and the lateral surface of the second dielectric layer is not coplanar with a lateral surface of the second metal layer (as seen in Fig. 11, the lower surface of 20 is not coplanar with a lower surface of 46).
Allowable Subject Matter
Claim 5 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: The prior art of record does not teach or fairly suggest the semiconductor testing structure as recited in the claims of the instant application.
Regarding claim 5, the prior art of Sills et al. (US 8,021,897 B2) in view of LiCausi (US 10,677,855 B2) in view of Kato et al. (US 9,431,412 B1) discloses a similar semiconductor testing structure but fails to disclose the specific claims of the instant application regarding the geometry of the interface between the first and second dielectric layers e.g. “wherein the first dielectric layer has a first upper surface in contact with the second dielectric layer and a second upper surface recessed from the first upper surface”.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BENJAMIN M KUPP whose telephone number is (571)272-5608. The examiner can normally be reached Monday - Friday, 7:00 am - 4:00 pm PT.
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/BENJAMIN MICHAEL KUPP/Examiner, Art Unit 2893
/YARA B GREEN/Supervisor Patent Examiner, Art Unit 2893
Prosecution Insights