Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAIL ACTION
2. The instant application having application No. 19/235,440 has a total of 13 claims pending in the application; there are 3 independent claim and 10 dependent claims, all of which are ready for examination by the examiner.
ACKNOWLEDGEMENT OF REFERENCES CITED BY APPLICANT
Information Disclosure Statement
3. As required by M.P.E.P. 2001.06(b) and 37 C.F.R. 1.98(d), since the instant application has been identified as a continuation application of an earlier filed application and is relied upon for an earlier filing date under 35 U.S.C. 120, the examiner has reviewed the prior art cited in the earlier related application as required by M.P.E.P. 707.05 and 904 and as stated in M.P.E.P. 2001.06(b), no separate citation of the same prior art need be made by the applicants in the instant application.
IFORMATION CONCENING IDS:
4. The information disclosure statements (IDS’) submitted on 06/11/2025 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement has been considered by the Examiner. A copy of PTOL-1449 initialed and signed by the examiner is/are attached to the instant office action.
IFORMATION CONCENING DRAWING:
5. Application’s drawing submitted on 06/11/2025 are acceptable for examination purposes.
INFORMATION CONCERNING FOREIGN PRIORITY:
6. Acknowledgment is made of applicant’s claim for foreign priority based on an application fled in Republic of Korea on 07/08/2022.
RELEVANT PRIOR ART CITED BY THE EXAMINER:
7. The following prior art made of record and not relied upon is cited to establish the level of skill in the applicant’s art and those arts considered reasonably pertinent to applicant’s disclosure.
Sinha (US 2021/0034958 A1) teaches “…within a configurable CNN processor in accordance with some aspects of the disclosure. The main IOs are the write ports 602 and read ports 604. The other 10 interface is a register-module interface 606 responsible for configuring the intelligent memory buffer 600. Each read/write port (604, 602) is supported by a small first in first out data buffer (FIFO) (608, 610), effectively making the memory operations elastic. Similarly, each core compute element can include FIFOs at the inputs and outputs…” (par. 0116).
REINHARDT et al. (US 20210042260 A1) teaches “…a hardware accelerator that implements a vector-based data flow, and that includes a tensor-processing engine and a scalar-processing unit, the tensor-processing engine including: at least one tensor register file for storing tensors…” (claim 1 0049).
Tasinga et al. (US 20230144662 A1) teaches “…one or more processing cores (“cores”) 3510, one or more special function units (“SFUs”) 3512, one or more load/store units (“LSUs”) 3514, an interconnect network 3516, a shared memory/level one (“L1”) cache 3518, and/or any suitable combination thereof. In at least one embodiment, LSUs 3514 perform load of store operations corresponding to loading/storing data …” (par. 0519).
IFORMATION CONCENING CLAIMS:
Double Patenting
8. The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
9. Claims 1-13 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims1-12 of U.S. Patent No. 12,361,270 B2 (hereinafter “the patent”). Although the claims at issue are not identical, they are not patentably distinct from each other because some minor changes in claim language and order word or limitations in the claims do not makes the rejected claims in instant application patentability distinct from the parent claims.
10. Claims of the instant application compared with claims of the parent in the following table:
US Patent 12,361,270 B2
US Application 19/235,440
1.A neural core comprising: a processing unit configured to perform operations; an L0 memory configured to store input data,
wherein the input data comprises a plurality of parts and a number of data granules of each of the plurality of parts is identical to each other; and
a load/store unit (LSU) configured to perform a load task and a store task of data between the processing unit and the L0 memory, wherein the LSU comprises a local memory load unit configured to transmit the input data in the L0 memory to the processing unit, and the local memory load unit configured to retrieve the input data in the L0 memory, transform an order of data granules of the input data based on an instruction and thereby generate transformed data, and transmit the transformed data to the processing unit,
wherein the instruction is a shuffle operation instruction that generates the transformed data in which the order of data granules of the input data is changed by sequentially and alternately arranging the data granules of each of the plurality of parts.
3. The neural core of claim 1,
wherein the input data has a size of an even multiple of one of the data granules.
A neural core comprising: a processing unit configured to perform operations; an L0 memory configured to store input data; and
a load/store unit (LSU) configured to perform a load task and a store task of data between the processing unit and the L0 memory, wherein the LSU comprises a local memory load unit configured to transmit the input data in the L0 memory to the processing unit, and the local memory load unit configured to retrieve the input data in the L0 memory, transform an order of data granules of the input data based on an instruction and thereby generate transformed data, and transmit the transformed data to the processing unit,
wherein the input data has a size of an even multiple of one of the data granules.
1.A neural core comprising: a processing unit configured to perform operations; an L0 memory configured to store input data,
wherein the input data comprises a plurality of parts and a number of data granules of each of the plurality of parts is identical to each other; and
a load/store unit (LSU) configured to perform a load task and a store task of data between the processing unit and the L0 memory, wherein the LSU comprises a local memory load unit configured to transmit the input data in the L0 memory to the processing unit, and the local memory load unit configured to retrieve the input data in the L0 memory, transform an order of data granules of the input data based on an instruction and thereby generate transformed data, and transmit the transformed data to the processing unit,
wherein the instruction is a shuffle operation instruction that generates the transformed data in which the order of data granules of the input data is changed by sequentially and alternately arranging the data granules of each of the plurality of parts.
2. The neural core of claim 1,
wherein the input data comprise first to j-th data granules of same size each other, and the transformed data comprises first to j-th data granules of same size each other, the processing unit receives the i input data simultaneously, and said j is an integer multiple of said i.
2. The neural core of claim 1,
wherein the input data comprises a plurality of parts, a number of data granules of each of the plurality of parts is identical to each other, and
the instruction is a shuffle operation instruction that generates the transformed data in which the order of data granule of the input data is changed by sequentially and alternately arranging the data granules of each of the plurality of parts,
wherein the input data comprise first to j-th data granules of same size each other, and the transformed data comprises first to j-th data granules of same size each other, the processing unit receives the i input data simultaneously, and said j is an integer multiple of said i.
4. The neural core of claim 3,
wherein the input data is i times larger than one of the data granules at most, the processing unit receives i input data simultaneously, and said i is a natural number.
3. The neural core of claim 1,
wherein the input data is i times larger than one of the data granules at most, the processing unit receives i input data simultaneously, and said i is a natural number.
5. The neural core of claim 1,
wherein the local memory load unit comprises: a target decision module configured to decode the instruction and identify the input data within the L0 memory, a transformation logic configured to perform the shuffle operation based on the instruction, and
an output first in first out (FIFO) configured to transmit the transformed data to the processing unit based on the instruction.
4. The neural core of claim 1,
wherein the local memory load unit comprises: a target decision module configured to decode the instruction and identify the input data within the L0 memory, a transformation logic configured to perform a merge operation or a shuffle operation based on the instruction, and
an output first in first out (FIFO) configured to transmit the transformed data to the processing unit based on the instruction.
6. The neural core of claim 5,
wherein the local memory load unit further comprises a tensor register file configured to receive the input data from the target decision module, provide the input data to the transformation logic, and receive the transformed data from the transformation logic.
5. The neural core of claim 4,
wherein the local memory load unit further comprises a tensor register file configured to receive the input data from the target decision module, provide the input data to the transformation logic, and receive the transformed data from the transformation logic.
7. The neural core of claim 6,
wherein the tensor register file has i entries, a number of FIFOs of the output FIFO is i, and said i is a natural number.
6. The neural core of claim 5, wherein the tensor register file has i entries, a number of FIFOs of the output FIFO is i, and said i is a natural number.
8. The neural core of claim 1,
wherein the instruction comprises a layout transform instruction for transforming a layout of the input data.
7. The neural core of claim 1,
wherein the instruction comprises a layout transform instruction for transforming a layout of the input data.
9. A neural processing device comprising:
at least one neural processor; a shared memory shared by the at least one neural processor; and a global interconnection configured to transmit data between the at least one neural processor and the shared memory, wherein each of the at least one neural processor comprises: at least one neural core; and an L1 shared memory shared by the at least one neural core, wherein the at least one neural core comprises: a processing unit configured to perform operations;
an LSU configured to transmit input data to the processing unit,
wherein the input data comprises a plurality of parts and a number of data granules of each of the plurality of parts is identical to each other; and
an L0 memory configured to store the input data, and wherein the LSU transforms an order of data granules of the input data based on an instruction, thereby generating transformed data, and transfers the transformed data to the processing unit, wherein the instruction is a shuffle operation instruction that generates the transformed data in which the order of data granules of the input data is changed by sequentially and alternately arranging the data granules of each of the plurality of parts.
3. The neural core of claim 1,
wherein the input data has a size of an even multiple of one of the data granules.
8. A neural processing device comprising:
at least one neural processor; a shared memory shared by the at least one neural processor; and a global interconnection configured to transmit data between the at least one neural processor and the shared memory, wherein each of the at least one neural processor comprises: at least one neural core; and an L1 shared memory shared by the at least one neural core, wherein the at least one neural core comprises: a processing unit configured to perform operations;
an LSU configured to transmit input data to the processing unit; and
an L0 memory configured to store the input data, and wherein the LSU transforms an order of data granules of the input data based on an instruction, thereby generating transformed data, and transfers the transformed data to the processing unit,
wherein the input data has a size of an even multiple of one of the data granules.
9. A neural processing device comprising:
at least one neural processor; a shared memory shared by the at least one neural processor; and a global interconnection configured to transmit data between the at least one neural processor and the shared memory, wherein each of the at least one neural processor comprises: at least one neural core; and an L1 shared memory shared by the at least one neural core, wherein the at least one neural core comprises: a processing unit configured to perform operations;
an LSU configured to transmit input data to the processing unit,
wherein the input data comprises a plurality of parts and a number of data granules of each of the plurality of parts is identical to each other; and
an L0 memory configured to store the input data, and wherein the LSU transforms an order of data granules of the input data based on an instruction, thereby generating transformed data, and transfers the transformed data to the processing unit, wherein
the instruction is a shuffle operation instruction that generates the transformed data in which the order of data granules of the input data is changed by sequentially and alternately arranging the data granules of each of the plurality of parts.
9. The neural processing device of claim 8,
wherein the input data comprises a plurality of parts, a number of data granules of each of the plurality of parts is identical to each other, and
the instruction is a shuffle operation instruction that generates the transformed data in which the order of data granule of the input data is changed by sequentially and alternately arranging the data granules of each of the plurality of parts.
10. The neural processing device of claim 9,
wherein the input data comprise first to j-th data granules of same size each other, and the transformed data comprises first to j-th data granules of same size each other, the processing unit receives the i input data simultaneously, and said j is an integer multiple of said i.
10. The neural processing device of claim 8,
wherein the input data comprise first to j-th data granules of same size each other, and the transformed data comprises first to j-th data granules of same size each other, the processing unit receives the i input data simultaneously, and said j is an integer multiple of said i.
11. A method for loading data of a neural processing device, comprising: receiving a layout transform instruction; storing input data in a tensor register file,
wherein the input data comprises a plurality of parts and a number of data granules of each of the plurality of parts is identical to each other;
transforming an order of data granules of the input data based on an instruction, thereby generating transformed data, wherein the instruction is a shuffle operation instruction that generates the transformed data in which the order of data granules of the input data is changed by sequentially and alternately arranging the data granules of each of the plurality of parts;
storing the transformed data in an output FIFO; and transferring the transformed data to a processing unit.
3. The neural core of claim 1,
wherein the input data has a size of an even multiple of one of the data granules.
11. A method for loading data of a neural processing device, comprising: receiving a layout transform instruction; storing input data in a tensor register file;
transforming an order of data granules of the input data based on an instruction, thereby generating transformed data;
storing the transformed data in an output FIFO; and transferring the transformed data to a processing unit,
wherein the input data has a size of an even multiple of one of the data granules.
12. The method for loading data of the neural processing device of claim 11, further comprising: storing the transformed data in the tensor register file after generating the transformed data; and transmitting the transformed data stored in the tensor register file to the output FIFO.
12. The method for loading data of the neural processing device of claim 11, further comprising: storing the transformed data in the tensor register file after generating the transformed data; and transmitting the transformed data stored in the tensor register file to the output FIFO.
11. A method for loading data of a neural processing device, comprising: receiving a layout transform instruction; storing input data in a tensor register file,
wherein the input data comprises a plurality of parts and a number of data granules of each of the plurality of parts is identical to each other;
transforming an order of data granules of the input data based on an instruction, thereby generating transformed data, wherein
the instruction is a shuffle operation instruction that generates the transformed data in which the order of data granules of the input data is changed by sequentially and alternately arranging the data granules of each of the plurality of parts;
storing the transformed data in an output FIFO; and transferring the transformed data to a processing unit.
13. The method of claim 11,
wherein the input data comprises a plurality of parts, a number of data granules of each of the plurality of parts is identical to each other, and
the instruction is a shuffle operation instruction that generates the transformed data in which the order of data granule of the input data is changed by sequentially and alternately arranging the data granules of each of the plurality of parts.
DIRECTION OF FUTURE CORRESPENDENCES:
25. Any inquiry concerning this communication or earlier communications from the examiner should be directed to HASHEM FARROKH whose telephone number is (571)272-4193. The examiner can normally be reached Monday through Friday from 8:30 am - 5:00 pm.
26. If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Mr. Tim Vo can be reached on (571)272-3642. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/HASHEM FARROKH/Primary Examiner, Art Unit 2138
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