Prosecution Insights
Last updated: October 02, 2026
Application No. 19/243,074

THERMAL BARRIER STRUCTURE IN PHASE CHANGE MATERIAL DEVICE

Non-Final OA §102§103
Filed
Jun 19, 2025
Priority
Oct 17, 2022 — provisional 63/416,645 +1 more
Examiner
TAN, DAVE
Art Unit
2897
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Taiwan Semiconductor Manufacturing Company, Ltd.
OA Round
1 (Non-Final)
81%
Grant Probability
Favorable
1-2
OA Rounds
2y 1m
Est. Remaining
73%
With Interview

Examiner Intelligence

Grants 81% — above average
81%
Career Allowance Rate
13 granted / 16 resolved
+13.3% vs TC avg
Minimal -8% lift
Without
With
+-8.3%
Interview Lift
resolved cases with interview
Typical timeline
3y 4m
Avg Prosecution
24 currently pending
Career history
41
Total Applications
across all art units

Statute-Specific Performance

§103
76.4%
+36.4% vs TC avg
§102
20.7%
-19.3% vs TC avg
§112
2.1%
-37.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 16 resolved cases

Office Action

§102 §103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claim(s) 1, 2, 5, 6, 9, 14, and 15 is/are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Slovin et al, US 20200058853. Regarding claim 1, Slovin discloses : An integrated chip, comprising: a heater structure overlying a semiconductor substrate(Fig. 1c, #102 over #114); a phase change element (PCE) disposed over the heater structure(Fig. 6c, #118 over #102); and a thermal barrier structure disposed between the heater structure and the PCE(#116 between #118 and #102), wherein outer sidewalls of the PCE are spaced laterally between outer sidewalls of the thermal barrier structure(#118 between sidewalls of #116). Regarding claim 2, Slovin discloses : The integrated chip of claim 1, wherein the thermal barrier structure comprises a first outer heater segment, a second outer heater segment(Fig 1a and 2a, #116(also #117) over #106 and #108 [0028-0029]), and a middle heater segment continuously laterally extending from the first outer heater segment to the second outer heater segment(#108 and #106 connected end to end through 104), wherein widths of the first and second outer heater segments are greater than a width of the middle heater segment(#108 may be larger than #104 [0020]). Regarding claim 5, Slovin discloses : The integrated chip of claim 2, further comprising: a first conductive structure overlying the semiconductor substrate(Fig. 6a, #130 top); and a second conductive structure overlying the semiconductor substrate(#130 bottom), wherein the first and second conductive structures are disposed on opposing sides of the middle heater segment(#130 disposed on opposing sides of #104), wherein the PCE directly overlies outer regions of the first and second conductive structures(#118 over out regions around #130). Regarding claim 6, Slovin discloses : The integrated chip of claim 1, wherein when viewed from above the heater structure and the thermal barrier structure have a first shape and the PCE has a second shape different from the first shape(Fig. 4a, #118 different shape than #102 with #116 overlying #102), wherein an area of the heater structure is less than an area of the thermal barrier structure(#116 may be any shape from #117a-#117c where #102 is less than an area of #117a and #117b [0029]). Regarding claim 9, Slovin discloses : An integrated chip, comprising: a lower dielectric layer overlying a semiconductor substrate(Fig. 1c, #110 over #114); a heater structure disposed within the lower dielectric layer(#102 in #110), wherein the heater structure comprises a middle heater segment(#104); a phase change element (PCE) overlying the heater structure(Fig. 4c, #118 over #102); and a thermal barrier structure vertically between the heater structure and the PCE(#116 between #102 and #118), wherein the thermal barrier structure continuously laterally extends from an outer edge of the PCE to directly over an outer region of the middle heater segment(Fig. 2a, #116 may cover any area #117a-#117c). Regarding claim 14, Slovin discloses: The integrated chip of claim 9, wherein when viewed from above the PCE and the thermal barrier structure have a first shape(Fig. 2a, #116 may have any shape from #117a-#117c [0029]) and the heater structure has a second shape different from the first shape(#102 is a different shape than #117a), wherein an area of the thermal barrier structure is greater than an area of the PCE(#117a has a greater area than #118 of Fig. 4a). Regarding claim 15, Slovin discloses : The integrated chip of claim 9, wherein the heater structure further comprises a first outer heater segment and a second outer heater segment disposed on opposing sides of the middle heater segment(#108 on opposing sides of #104), wherein the first and second outer heater segments each have two or more discrete widths greater than a width of the middle heater segment(#108 may have any size or shape where #108 is a greater area than #104 [0020]). Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 3 and 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Slovin et al, US 20200058853. Regarding claim 3, Slovin discloses : The integrated chip of claim 2. Slovin does not disclose : wherein the PCE directly overlies the middle heater segment and wherein a length of the middle heater segment is greater than a length of the PCE. However, Slovin teaches : wherein the PCE directly overlies the middle heater segment and wherein a length of the middle heater segment is greater than a length of the PCE(#120 determines channel area of layers #118 [0036]). It would have been an obvious matter of design choice to adjust the size of the mask so that after a patterning process a middle segment of the heater is greater in length than the PCE, since such a modification would have involved a mere change in the size of component. A change in size is generally recognized as being within the level of ordinary skill in the art. In re Rose, 105 USPQ 237 (CCPA 1955). See MPEP 2144.04. Regarding claim 4, Slovin discloses : The integrated chip of claim 3, wherein a width of the PCE is greater than the width of the middle heater segment(Fig. 6a, #118 has a larger width than #104). Claim(s) 7, 8, and 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Slovin et al, US 20200058853 in view of Li et al, US 20220285614. Regarding claim 7, Slovin discloses : The integrated chip of claim 1. Slovin does not disclose : further comprising: a sidewall spacer structure disposed on the outer sidewalls of the PCE, wherein the sidewall spacer structure contacts a top surface of the thermal barrier structure. However, in the same field of endeavor, Li teaches : a sidewall spacer structure disposed on the outer sidewalls of the PCE(Fig. 7a, #77 on sidewalls of #43), wherein the sidewall spacer structure contacts a top surface of the thermal barrier structure(#77 contacting #11). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teachings of Li to Slovin to protect a phase change material (Li [0044]). Regarding claim 8, Slovin as modified by Li discloses : The integrated chip of claim 7. Li teaches : wherein the sidewall spacer structure and the thermal barrier structure respectively comprise a non-oxygen based dielectric material(#77 may be tungsten [0070] and #11 may be silicon nitride [0058]). Regarding claim 10, Slovin discloses : The integrated chip of claim 9. Slovin does not disclose : further comprising: a sidewall spacer structure laterally wrapped around the PCE, wherein the sidewall spacer structure directly overlies at least a portion of the outer region of the middle heater segment. However, in the same field of endeavor, Li teaches : a sidewall spacer structure laterally wrapped around the PCE(Fig. 1, #77), wherein the sidewall spacer structure directly overlies at least a portion of the outer region of the middle heater segment(#77 overlies portions of #80b). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teachings of Li to Slovin to protect a phase change material (Li [0044]). Claim(s) 11-13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Slovin et al, US 20200058853 in view of Li et al, US 20220285614 in further view of Yu et al, US 20200136033. Regarding claim 11, Slovin as modified by Li discloses : The integrated chip of claim 10. Slovin as modified by Li does not disclose : further comprising: a capping layer overlying the PCE, wherein the capping layer continuously extends from over the PCE, along sidewalls of the sidewall spacer structure, to a top surface of the heater structure. However, in the same field of endeavor, Yu teaches : a capping layer overlying the PCE(Fig. 1a, #128), wherein the capping layer continuously extends from over the PCE(#128 extending over #120), along sidewalls of the sidewall spacer structure(#128 along sidewalls of #126), to a top surface of the heater structure(#128 extending over #108). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teachings of Yu to Slovin and Li to include a capping layer to prevent voids during a manufacturing process (Yu [0017]). Regarding claim 12, Slovin as modified by Li discloses : The integrated chip of claim 10. Slovin as modified by Li does not disclose : further comprising: a hard mask disposed on the PCE, wherein the sidewall spacer structure continuously extends from opposing sidewalls of the PCE to opposing sidewalls of the hard mask. However, in the same field of endeavor, Yu teaches : further comprising: a hard mask disposed on the PCE(Fig. 1a, #124), wherein the sidewall spacer structure continuously extends from opposing sidewalls of the PCE to opposing sidewalls of the hard mask(#126 extending from sidewall of #120 to sidewall of #124). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teachings of Yu to Slovin and Li to include a hard mask to provide alignment during a manufacturing process(Yu [0047]). Regarding claim 13, Slovin as modified by Li and Yu discloses : The integrated chip of claim 12. Yu teaches : wherein a top surface of the hard mask is aligned with a top surface of the sidewall spacer structure(Fig. 1a, top surfaces of #124 and #126 are aligned). Claim(s) 21-25 is/are rejected under 35 U.S.C. 103 as being unpatentable over Slovin et al, US 20200058853 in view of Yu et al, US 20200136033. Regarding claim 21, Slovin discloses : An integrated chip, comprising: a heater structure overlying a semiconductor substrate(Fig. 6c, #102), wherein the heater structure comprises a first outer segment, a second outer segment(#108), and a middle segment extending between the first and second outer segments(#104); a first conductive structure and a second conductive structure overlying the semiconductor substrate and spaced on opposing sides of the middle segment(Fig. 6a, #130); a phase change element (PCE) overlying the middle segment(#118), and a thermal barrier structure between the middle segment and the PCE(#116 between #104 and #118), wherein the thermal barrier structure comprises a first peripheral segment extending from the first sidewall towards the first outer segment and a second peripheral segment extending from the second sidewall towards the second outer segment(#116 over #106 and #108). Slovin does not disclose : wherein the PCE comprises a first sidewall and a second sidewall spaced between the first and second outer segments in a first cross-sectional view. However, in the same field of endeavor, Yu teaches : wherein the PCE comprises a first sidewall and a second sidewall spaced between the first and second outer segments in a first cross-sectional view(Fig. 1a, #126 outside of sidewalls of #114). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teachings of Yu to Slovin to include sidewall spacers to protect a phase change element (Yu [0016]). Regarding claim 22, Slovin as modified by Yu discloses : The integrated chip of claim 21. Slovin teaches : wherein lengths of the first and second peripheral segments are greater than a thickness of the thermal barrier structure(Fig. 6c, #116 may be five hundred angstroms to approximately five thousand angstroms [0031] and #106 shown to be greater in length than the thickness of #116). It would have been an obvious matter of design choice to adjust a length of the peripheral segments to be greater than a thickness of a thermal barrier layer, since such a modification would have involved a mere change in the size of component. A change in size is generally recognized as being within the level of ordinary skill in the art. In re Rose, 105 USPQ 237 (CCPA 1955). See MPEP 2144.04. Regarding claim 23, Slovin as modified by Yu discloses : The integrated chip of claim 21. Slovin teaches : wherein in a second cross-sectional view a width of the thermal barrier structure over the middle segment is less than a width of the PCE, wherein the second cross-sectional view is orthogonal to the first cross- sectional view(Fig. 6b, #116 over #104 less than width of #118). Regarding claim 24, Slovin as modified by Yu discloses : The integrated chip of claim 23. Slovin teaches : wherein the width of the thermal barrier structure is less than a width of the first outer segment and a width of the second outer segment(#108 may have any size or shape [0020] and #116 may be five hundred angstroms to approximately five thousand angstroms [0031]). It would have been an obvious matter of design choice to adjust a width of a thermal barrier structure to be less than a width of the outer segments, since such a modification would have involved a mere change in the size of component. A change in size is generally recognized as being within the level of ordinary skill in the art. In re Rose, 105 USPQ 237 (CCPA 1955). See MPEP 2144.04. Regarding claim 25, Slovin as modified by Yu discloses : The integrated chip of claim 21. Slovin teaches : wherein the first peripheral segment overlies the first outer segment and the second peripheral segment overlies the second outer segment(Fig. 2a, #117a [0029]), wherein thicknesses of the first and second peripheral segments are less than a thickness of the thermal barrier structure over the middle segment(#116 can be non-planar with a thickness of approximately five hundred angstroms to approximately five thousand angstroms [0031]). It would have been an obvious matter of design choice to adjust a thickness of the thermal barrier structure, since such a modification would have involved a mere change in the size of component. A change in size is generally recognized as being within the level of ordinary skill in the art. In re Rose, 105 USPQ 237 (CCPA 1955). See MPEP 2144.04. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: US 20140264230 – Phase change material switch. Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVE TAN whose telephone number is (571)272-6841. The examiner can normally be reached M-F: 8-4 PST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, CHAD DICKE can be reached at (571) 270-7996. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /D.T./Examiner, Art Unit 2897 /CHAD M DICKE/Supervisory Patent Examiner, Art Unit 2897
Read full office action

Prosecution Timeline

Jun 19, 2025
Application Filed
Nov 06, 2025
Response after Non-Final Action
Aug 25, 2026
Non-Final Rejection mailed — §102, §103 (current)

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Prosecution Projections

1-2
Expected OA Rounds
81%
Grant Probability
73%
With Interview (-8.3%)
3y 4m (~2y 1m remaining)
Median Time to Grant
Low
PTA Risk
Based on 16 resolved cases by this examiner. Grant probability derived from career allowance rate.

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