Prosecution Insights
Last updated: April 19, 2026
Application No. 19/254,022

SCANNING CIRCUIT, DISPLAY PANEL AND DISPLAY DEVICE

Non-Final OA §103
Filed
Jun 30, 2025
Examiner
YANG, NAN-YING
Art Unit
2629
Tech Center
2600 — Communications
Assignee
Wuhan Tianma Microelectronics Co., Ltd.
OA Round
1 (Non-Final)
77%
Grant Probability
Favorable
1-2
OA Rounds
2y 1m
To Grant
86%
With Interview

Examiner Intelligence

Grants 77% — above average
77%
Career Allow Rate
629 granted / 815 resolved
+15.2% vs TC avg
Moderate +9% lift
Without
With
+8.9%
Interview Lift
resolved cases with interview
Fast prosecutor
2y 1m
Avg Prosecution
16 currently pending
Career history
831
Total Applications
across all art units

Statute-Specific Performance

§101
1.5%
-38.5% vs TC avg
§103
74.1%
+34.1% vs TC avg
§102
10.3%
-29.7% vs TC avg
§112
7.7%
-32.3% vs TC avg
Black line = Tech Center average estimate • Based on career data from 815 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1, 18 and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yan et al. (US. Pub. No. 2023/0395008, hereinafter “Yan”) in view of Chien et al. (US. Pub. No. 2014/0219412, hereinafter “Chien”). As to claim 1, Yan discloses a scanning circuit [figures 6-9, scan circuit], comprising at least a plurality of cascaded first shift register units [figures 6-9, a plurality of cascaded first shift register units SR], wherein at least one of the plurality of first shift register units comprises: a first input module [figures 2-3, input circuit 11 comprising an input terminal to receive a first trigger signal INP] comprising an input terminal configured to receive a first trigger signal; a first cascade module [figures 2-3, cascade circuit 20 comprising an output terminal to output a first cascade signal GO] comprising an output terminal configured to output a first cascade signal; and a first stabilizing switch module [figures 2-3, stabilization circuit 14], wherein an output terminal of the first stabilizing switch module is electrically connected to an output terminal of the first input module; and/or wherein the output terminal of the first stabilizing switch module is electrically connected to part of control terminals of the first cascade module [figure 3, output terminal of circuit 14 is electrically connected to part of control terminals of cascade module 20 (control terminal of M1)]. Yan does not expressly disclose a voltage-stabilizing switch module. Chien teaches a voltage-stabilizing switch module [figure 3, a voltage stabilizing circuit 180]. Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to have modified the scanning circuit of Yan to use a voltage-stabilizing switch module, as taught by Chien, in order to ensure stability of voltage levels within the stage so to avoid trigger errors on the shift register (Chien, paragraph 9). As to claim 18, Yan discloses a display panel [figure 10, a display device with a display panel], comprising a scanning circuit [figures 6-9, scan circuit], wherein the scanning circuit comprises at least a plurality of cascaded first shift register units [figures 6-9, a plurality of cascaded first shift register units SR], and at least one of the plurality of first shift register units comprises: a first input module [figures 2-3, input circuit 11 comprising an input terminal to receive a first trigger signal INP] comprising an input terminal configured to receive a first trigger signal; a first cascade module [figures 2-3, cascade circuit 20 comprising an output terminal to output a first cascade signal GO] comprising an output terminal configured to output a first cascade signal; and a first stabilizing switch module [figures 2-3, stabilization circuit 14]; wherein an output terminal of the first stabilizing switch module is electrically connected to an output terminal of the first input module; and/or wherein the output terminal of the first stabilizing switch module is electrically connected to part of control terminals of the first cascade module [figure 3, output terminal of circuit 14 is electrically connected to part of control terminals of cascade module 20 (control terminal of M1)]. Yan does not expressly disclose a voltage-stabilizing switch module. Chien teaches a voltage-stabilizing switch module [figure 3, a voltage stabilizing circuit 180]. Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to have modified the scanning circuit of Yan to use a voltage-stabilizing switch module, as taught by Chien, in order to ensure stability of voltage levels within the stage so to avoid trigger errors on the shift register (Chien, paragraph 9). As to claim 19, Yan discloses a display device [figure 10, a display device with a display panel], comprising a display panel, wherein the display panel comprises a scanning circuit [figures 6-9, scan circuit], the scanning circuit comprises at least a plurality of cascaded first shift register units [figures 6-9, a plurality of cascaded first shift register units SR], and at least one of the plurality of first shift register units comprises: a first input module [figures 2-3, input circuit 11 comprising an input terminal to receive a first trigger signal INP] comprising an input terminal configured to receive a first trigger signal; a first cascade module [figures 2-3, cascade circuit 20 comprising an output terminal to output a first cascade signal GO] comprising an output terminal configured to output a first cascade signal; and a first stabilizing switch module [figures 2-3, stabilization circuit 14]; wherein an output terminal of the first stabilizing switch module is electrically connected to an output terminal of the first input module; and/or wherein the output terminal of the first stabilizing switch module is electrically connected to part of control terminals of the first cascade module [figure 3, output terminal of circuit 14 is electrically connected to part of control terminals of cascade module 20 (control terminal of M1)]. Yan does not expressly disclose a voltage-stabilizing switch module. Chien teaches a voltage-stabilizing switch module [figure 3, a voltage stabilizing circuit 180]. Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to have modified the scanning circuit of Yan to use a voltage-stabilizing switch module, as taught by Chien, in order to ensure stability of voltage levels within the stage so to avoid trigger errors on the shift register (Chien, paragraph 9). Allowable Subject Matter Claims 2-17 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: None of the prior art, made of record, singularly or in combination, teaches or fairly suggests the features presented in the combination limitations of dependent claims 2 and 10, such as “wherein the first input module further comprises an output terminal electrically connected to a first node, and a control terminal configured to receive a first clock signal, the first cascade module further comprise a first input terminal configured to receive a first fixed potential signal, a second input terminal configured to receive a second fixed potential signal, and the control terminals electrically connected to a second node; wherein at least one first shift register unit further comprises a first control module, the first control module comprises a first input terminal configured to receive the first fixed potential signal, a second input terminal configured to receive the second fixed potential signal, a control terminal electrically connected to the first node, and an output terminal electrically connected to the second node; and wherein the first voltage-stabilizing switch module comprises an input terminal configured to receive the second fixed potential signal, the output electrically connected to the first node, and a control terminal electrically connected to the second node”, recited by claim 2; and “wherein the first input module has a first output terminal electrically connected to a primary node, a second output terminal electrically connected to a secondary node, and a control terminal configured to receive a first clock signal, the primary node is coupled to a second primary node, and the first secondary node is coupled to a second secondary node; wherein the first cascade module comprises a first cascade sub-module and a second cascade sub-module; the first cascade sub-module comprises an input terminal configured to receive the first fixed potential signal, an output terminal electrically connected to the output terminal of the first cascade module, and a control terminal electrically connected to a third node; and the second cascade sub-module comprises an input terminal configured to receive the second fixed potential signal, an output terminal electrically connected to the output terminal of the first cascade module, and a control terminal electrically connected to the second primary node; wherein at least one first shift register unit further comprises a first control module, the first control module comprises a first control sub-module and a second control sub-module, the first control sub-module comprises an input terminal configured to receive the first fixed potential signal, an output terminal electrically connected to the third node, and a control terminal electrically connected to the first primary node; and the second control sub-module comprises an input terminal configured to receive the second fixed potential signal, an output terminal electrically connected to the third node, and a control terminal electrically connected to the second primary node; and wherein the first voltage-stabilizing switch module comprises an input terminal electrically connected to the second secondary node, an output terminal electrically connected to the second primary node, and a control terminal electrically connected to the second secondary node”, recited by claim 10. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US. Pub. No. 2006/0028461 (Lu et al.) is considered as pertinent art as seen in figure 4. US. Pub. No. 2006/0187177 (Kuo et al.) is also considered as pertinent art as seen in figure 4. Any inquiry concerning this communication or earlier communications from the examiner should be directed to NAN-YING YANG whose telephone number is (571)272-2211. The examiner can normally be reached Monday-Friday, 8am-5pm, EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, BENJAMIN LEE can be reached at (571)272-2963. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /NAN-YING YANG/ Primary Examiner, Art Unit 2629
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Prosecution Timeline

Jun 30, 2025
Application Filed
Feb 20, 2026
Non-Final Rejection — §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

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2y 5m to grant Granted Apr 14, 2026
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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
77%
Grant Probability
86%
With Interview (+8.9%)
2y 1m
Median Time to Grant
Low
PTA Risk
Based on 815 resolved cases by this examiner. Grant probability derived from career allow rate.

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