DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Regarding claim 3, line 2 recites, “dispensing a underfill the LSI die and the redistribution structure.” This seemingly lacks a required preposition to identify the position/location of the underfill, thus making the claim indefinite. Examiner suggests providing the appropriate preposition, such as “between” to clarify the meaning of the location of the underfill commensurate with the specification and drawings.
Regarding claim 10, lines 2-3 recite, “on between the LSI die and the passive device die.” A double preposition leads to an indefinite meaning pertaining to the location of the external connectors. Examiner suggests removing “on” in order to provide clarity concerning this limitation commensurate with the specification and drawings.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim 16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yu et al. (2020/0176387, hereafter Yu ‘387).
Regarding claim 16, Yu ‘387 discloses a method comprising: bonding a first package component (100) to a substrate (302) using a first plurality of connectors (138B/164), wherein the first package component comprises: a first integrated circuit die (50 left) and a second integrated circuit die (50 right) in a molding compound (120, Fig. 20, par. 0031); a redistribution structure (122) electrically connected to the first integrated circuit die and the second integrated circuit die; and a third die (146) on an opposing side of the redistribution structure as the first integrated circuit die and the second integrated circuit die, wherein the third die is disposed on a same surface of the redistribution structure as the first plurality of connectors, and wherein the third die is a local silicon interconnect (LSI) die or a passive device die (par. 0042); and dispensing a first underfill (306) around the first plurality of connectors and the third die, wherein the first underfill extends continuously from a lateral surface of the third die to a lateral surface of the substrate (Fig. 23).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 6-8, and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Yu ‘387 in view of Yu et al. (2022/0199461, hereafter Yu ‘461).
Regarding claim 1, Yu ‘387 discloses a method, comprising: encapsulating a first die (50 left) and a second die (50 right) in an encapsulant (120, Fig. 20, par. 0031); forming a redistribution structure (122) over the encapsulant, the first die, and the second die; bonding a die (146) to a surface of the redistribution structure that is opposite to the first die, wherein the die is electrically connected to the first die and the second die through the redistribution structure; and forming a plurality of external connectors (138B/164) on the surface of the redistribution structure (Fig. 23).
Yu ‘387 fails to disclose that the die is a local silicon interconnect (LSI), wherein the plurality of external connectors extends further from the redistribution structure than the LSI die.
However, Yu ‘461 teaches that the die is a local silicon interconnect (LSI) (50, Fig. 16, par. 0019-0020), wherein the plurality of external connectors extends further from the redistribution structure than the LSI die (116, Fig. 9, par. 0029).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Yu ‘387 with Yu ‘461 by providing an LSI and connectors extending farther than the LSI in order to provide ultra-dense , low latency bridge connections without consuming surface area, while tall connectors allow the package to connect to external devices.
Regarding claim 2, Yu ‘387 discloses a method wherein the die (146) is bonded to the surface of the redistribution structure (122) using a plurality of solder connectors (par. 0011) (Fig. 23).
Yu ‘387 fails to disclose that the die is an LSI.
However, Yu ‘461 teaches that the die is an LSI (50, Fig. 16, par. 0019-0020).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Yu ‘387 with Yu ‘461 by providing an LSI in order to provide ultra-dense , low latency bridge connections without consuming surface area.
Regarding claim 3, Yu ‘387 discloses a method further comprising: dispensing a underfill (140) the die (146) and the redistribution structure (122) (Fig. 23).
Yu ‘387 fails to disclose that the die is an LSI, wherein the underfill extends partially up sidewalls of the LSI die.
However, Yu ‘461 teaches that the die is an LSI (50, par. 0019-0020), wherein the underfill (215) extends partially up sidewalls of the LSI die (Fig. 16).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Yu ‘387 with Yu ‘461 by providing an LSI and underfill extending up the sides in order to provide ultra-dense, low latency bridge connections without consuming surface area, while mitigating thermomechanical stress at interfaces and preventing moisture contamination.
Regarding claim 6, Yu ‘387 discloses a method further comprising: bonding a passive device die (146) to the surface of the redistribution structure (122) (Fig. 23).
Regarding claim 7, Yu ‘387 discloses a method wherein the passive device die (146) overlaps the first die (50 left) (Fig. 23).
Regarding claim 8, Yu ‘387 fails to disclose a method wherein a first external connector of the plurality of external connectors is disposed between the passive device die and the LSI die.
However, Yu ‘461 teaches a method wherein a first external connector of the plurality of external connectors (116 center) is disposed between the passive device die (80) and the LSI die (50) (Fig. 5).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Yu ‘387 with Yu ‘461 by providing connectors between the LSI and passive device in order to minimize parasitic inductance and latency by keeping direct routing paths to dies.
Regarding claim 17, Yu ‘387 discloses method wherein the first package component further comprises a second underfill (140) on the third die (146), wherein the first underfill surrounds the second underfill (Fig. 23).
Yu ‘387 fails to disclose a second underfill around the third die.
However, Yu ‘461 teaches a second underfill (215) around the third die (260) (Fig. 16).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Yu ‘387 with Yu ‘461 by providing an underfill around the die in order to encapsulate bumps and distribute stress, preventing contamination and protecting joints from failure.
Claims 4, 5, 9-15, and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Yu ‘387 in view of Yu ‘461 and Hong et al. (2020/0135698, hereafter Hong).
Regarding claim 4, Yu ‘387, discussed above, fails to disclose an LSI die.
However, Yu ‘461 teaches an LSI die (50, par. 0019-0020).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Yu ‘387 with Yu ‘461 by providing an LSI in order to provide ultra-dense , low latency bridge connections without consuming surface area.
Yu ‘387 further fails to disclose a method further comprising thinning the LSI die after bonding the LSI die to the surface of the redistribution structure.
However, Hong teaches a method further comprising thinning the LSI die after bonding the LSI die to the surface of the redistribution structure (par. 0129).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Yu ‘387 and Yu ‘461 with Hong by thinning the LSI in order to achieve uniform profiles, allowing for consistent molding and interconnections that are stress-free.
Regarding claim 5, Yu ‘387 fails to disclose an LSI die.
However, Yu ‘461 teaches an LSI die (50, par. 0019-0020).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Yu ‘387 with Yu ‘461 by providing an LSI in order to provide ultra-dense , low latency bridge connections without consuming surface area.
Yu ‘387 further fails to disclose a method, wherein thinning the die comprises planarizing a surface of the die to be level with a surface of the underfill.
However, Hong teaches a method, wherein thinning the die (40) comprises planarizing a surface of the die to be level with a surface of the underfill (60a) (Fig. 7D-7E, par. 0129).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Yu ‘387 and Yu ‘461 with Hong by performing a planarization process on the die to be level with the underfill in order to achieve uniform profiles, allowing for consistent molding and interconnections that are stress-free.
Regarding claim 9, Yu ‘387 discloses a method comprising: forming a redistribution structure (122) over and electrically connected to a first die (50 left) and a second die (50 righ) (Fig. 23).
Yu ’387 fails to disclose bonding a local silicon interconnect (LSI) die and a passive device die to an opposing side of the redistribution structure as the first die, wherein the LSI die is electrically connects the first die to the second die; dispensing a first underfill between the LSI die and the redistribution structure; dispensing a second underfill between and the passive device die and the redistribution structure.
However, Yu ‘461 teaches bonding a local silicon interconnect (LSI) die (50) and a passive device die (80) to an opposing side of the redistribution structure as the first die, wherein the LSI die is electrically connects the first die to the second die (Fig. 16); dispensing a first underfill between the LSI die and the redistribution structure (Fig. 16); dispensing a second underfill between and the passive device die and the redistribution structure (Fig. 16).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Yu ‘387 with Yu ‘461 by providing an LSI in order to provide ultra-dense, low latency bridge connections without consuming surface area and share routing connections to die, while mitigating thermomechanical stress at interfaces and preventing moisture contamination.
Yu ‘387 and Yu ‘461 fail to disclose performing a planarization process on a first surface the LSI die and a second surface of the passive device die that are opposite to the redistribution structure.
However, Hong teaches performing a planarization process on a first surface the LSI die and a second surface of the passive device die that are opposite to the redistribution structure (par. 0129).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Yu ‘387 and Yu ‘461 with Hong by performing a planarization process on the LSI and passive device in order to achieve uniform profiles, allowing for consistent molding and interconnections that are stress-free.
Regarding claim 10, Yu ‘387 fails to disclose a method further comprising: forming one or more external connectors on between the LSI die and the passive device die, wherein a height of the one or more external connectors is greater than a height of the LSI die and a height of the passive device die.
However, Yu ‘461 teaches a method further comprising: forming one or more external connectors on between the LSI die and the passive device die, wherein a height of the one or more external connectors is greater than a height of the LSI die and a height of the passive device die.
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Yu ‘387 with Yu ‘461 by providing connectors between the LSI and passive device in order to minimize parasitic inductance and latency by keeping direct routing paths to dies while tall connectors allow the package to connect to external devices.
Regarding claim 11, Yu ‘387 discloses a passive device die (146, Fig. 23)
Yu ‘387 fails to disclose an LSI die.
However, Yu ‘461 teaches an LSI die (50, Fig. 16).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Yu ‘387 with Yu ‘461 by providing an LSI in order to provide ultra-dense, low latency bridge connections without consuming surface area.
Yu ‘387 and Yu ‘461 fail to disclose a method wherein the planarization process levels the first surface of the die with the second surface of the device die.
However, Hong teaches a method wherein the planarization process (par. 0129) levels the first surface of the LSI die (40 left) with the second surface of the passive device die (40 right) (Fig. 7C – 7E).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Yu ‘387 and Yu ‘461 with Hong by performing a planarization process on the LSI and passive device in order to achieve uniform profiles, allowing for consistent molding and interconnections that are stress-free.
Regarding claim 12, Yu ‘387 fails to disclose an LSI die.
However, Yu ‘461 teaches an LSI die (50, par. 0019-0020).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Yu ‘387 with Yu ‘461 by providing an LSI in order to provide ultra-dense , low latency bridge connections without consuming surface area.
Yu ‘387 and Yu ‘461 fail to disclose a method wherein the planarization process levels the first surface of the die with the first underfill.
However, Hong teaches a method wherein the planarization process (par. 0129) levels the first surface of the LSI die (40) with the first underfill (60a) (Fig. 7D-7E).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Yu ‘387 and Yu ‘461 with Hong by performing a planarization process to match the height of the die and underfill in order to create a coplanar surface which ensures uniform contact for subsequent layer connections preventing void formation and thus mitigating stress.
Regarding claim 13, Yu ‘387 discloses a passive device die (146, Fig. 23).
Yu ‘387 and Yu ‘461 fail to disclose a method wherein the planarization process levels the second surface of the device die with the second underfill.
However, Hong teaches a method wherein the planarization process (par. 0129) levels the second surface of the passive device die (40) with the second underfill (60a) (Fig. 7D-7E).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Yu ‘387 and Yu ‘461 with Hong by performing a planarization process to match the height of the die and underfill in order to create a coplanar surface which ensures uniform contact for subsequent layer connections preventing void formation and thus mitigating stress.
Regarding claim 14, Yu ‘461 teaches an LSI die and passive device die, and Hong teaches a planarization process leveling the height of the die. Further, given that the planarization process levels the respective heights of the die, the prior heights of the die do not affect the function of the device. In Gardner v.TEC Syst., Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984), the Federal Circuit held that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device.
Regarding claim 15, Yu ‘387 fails to disclose an LSI die.
However, Yu ‘461 teaches an LSI die (50, par. 0019-0020).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Yu ‘387 with Yu ‘461 by providing an LSI in order to provide ultra-dense , low latency bridge connections without consuming surface area.
Yu ‘387 further fails to disclose a method wherein the first underfill surrounds the die in a plan view.
However, Yu ‘461 teaches a method wherein the first underfill (215, par. 0065) surrounds the die (260) in a plan view (Fig. 16).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Yu ‘387 with Yu ‘461 by providing underfill around the LSI in order to encapsulate bumps and distribute stress, preventing contamination and protecting joints from failure.
Regarding claim 18, Yu ‘387 and Yu ‘461 fail to disclose a method wherein the second underfill comprises a lateral surface at a same level as the lateral surface of the third die.
However, Hong teaches a method wherein the second underfill (60a/60b) comprises a lateral surface at a same level as the lateral surface of the third die (40) (Fig. 7D-7E, par. 0130).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Yu ‘387 and Yu ‘461 with Hong by providing an underfill at the same height as the die in order to prevent stress concentration and enable uniform contact for interconnections.
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Yu ‘387 in view of Choi et al. (2021/0272930, hereafter Choi).
Regarding claim 19, Yu ‘387, discussed above, fails to disclose a method further comprising attaching a conductive lid to a surface of the first package component opposite to the substrate.
However, Choi teaches a method further comprising attaching a conductive lid (920) to a surface of the first package component (2200) opposite to the substrate (100) (Fig. 20).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Yu ‘387 with Choi by providing a conductive lid in order to dissipate heat from the die and protecting the device from damage.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Yu ‘387 in view of Yu et al. (2018/0269188, hereafter Yu ‘188).
Regarding claim 20, Yu ‘387, discussed above, fails to disclose a method further comprising bonding a second package component to the substrate adjacent to the first package component.
However, Yu ‘188 teaches a method further comprising bonding a second package component (602) to the substrate (100) adjacent to the first package component (600) (Fig. 5, par. 0016).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Yu ‘387 with Yu ‘188 by providing a second package component on the substrate in order to enable efficient communication between dies while maintaining compactness.
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Wu et al. (20210202396), pertaining to presence of LSI.
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/C.M.B./ Examiner, Art Unit 2817
/MARLON T FLETCHER/ Supervisory Primary Examiner, Art Unit 2817
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