DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The prior art documents submitted by applicant in the Information Disclosure Statements filed on 07/10/2025, 10/29/2025, 02/17/2026 and 06/04/2026 have been considered and made of record.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 4, 10, 11 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over disclosed prior art, Jungho Do et al., (United States Patent Application Publication Number US 2022/0208757 A1) hereinafter referenced as Do_757.
Regarding claim 1, Do_757 teaches a method of manufacturing an integrated circuit (IC) device, the method comprising: fabricating at least one circuit over a substrate having opposite front and back sides (Fig.1, circuit, element #30, paragraph [0045], rows 1-2 is built over substrate, element #110, paragraph [0052], row 3 showed in Fig.4); fabricating a front side redistribution structure on the front side of the substrate (Fig.3, formed by metal layer #M1_L and #M2_L), the front side redistribution structure comprising a front side metal layer (Fig.3, metal layer #M1_L), which comprises: a first front side power rail (Fig.3, element #VDD, paragraph [0045], row 2) coupled to a first source/drain of a transistor of the at least one circuit (Fig.3, element #VVDD is coupled to SD), and a second front side power rail (Fig.3, element #VVDD on the top side of the image, paragraph [0045], row 4); coupled to a second source/drain of the transistor (Fig.3 and Fig.4, element #VDD is coupled to SD through elements #V2B, #M2L and #V2). In a different embodiment Do_757 teaches fabricating a plurality of feed through vias (FTVs) extending through the substrate, the plurality of FTVs comprising: a first FTV coupled to the first front side power rail (Fig.4, element #TVI, paragraph [0062], row 3), a second FTV coupled to the second front side power rail (Fig.27A, element #TV_S, paragraph [0140], row 6 is coupled to #VVDD).It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to combine the teachings of Do_757 and disclose fabricating a plurality of feed through vias (FTVs) extending through the substrate, the plurality of FTVs comprising: a first FTV coupled to the first front side power rail, a second FTV coupled to the second front side power rail. This allows power to be provided to both VDD and VVDD, through the back side of the substrate, which can be easily achieved using a circuit board coupled to the backside.
Do_757 further teaches fabricating a back side redistribution structure on the back side of the substrate (Fig.4, element #PWS), the back side redistribution structure comprising a back side metal layer (Fig.4, element #PWL1), which comprises: a first back side power rail coupled to the first FTV (Fig.4, element #PWL1 locate under #TVI), and a second back side power rail coupled to the second FTV (Fig.27A, element #PWL1 on the right side of the figure).
Regarding claim 2, Do_757 teaches the method of claim 1, as set forth in the obviousness rejection. Do_757 further teaches the method of claim 1, wherein the at least one circuit comprises a header circuit (Fig.1, element #30 it is used to for power gating to turned off power supplied to circuits) comprising the transistor which is a P- type transistor (Fig.1, element #PGT, paragraph [0049], rows 11-12).
Regarding claim 4, Do_757 teaches the method of claim 1, as set forth in the obviousness rejection. Do_757 further teaches the method of claim 1, wherein the at least one circuit comprises a functional circuit (Fig.1, element #20, paragraph [0053], rows 1-6), coupled to at least one of the second front side power rail by the front side redistribution structure (Fig.1, element #20, is coupled to #VVDD), or the second back side power rail by the back side redistribution structure (Fig.27 ,second frontside and backside power rails are coupled so element #20 is also coupled to backside power rail).
Regarding claim 10, Do_757 teaches the method of claim 1, as set forth in the obviousness rejection. Do_757 further teaches the method of claim 1, wherein the front side redistribution structure further comprises a further front side metal layer (Fig.4, element #M2L), the back side redistribution structure further comprises a further back side metal layer (Fig.4, element #PWL2), the front side metal layer (Fig.4, element #M1L) further comprises: a first front side conductive pattern (Fig.4, element #VDDG) coupled to the first front side power rail through the further front side metal layer (Fig.4, element #VDDG is coupled to element #VDD through element #M2L). In a separate embodiment, same as the second embodiment used in the rejection of claim 1, Do_757 teaches a second front side conductive pattern coupled to the second front side power rail through the further front side metal layer (Fig.27B, element #M1L on top of via element #TV_S is coupled to second front side power rail, element #VVDD, through element #M2L). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to combine the teachings of Do_757 and disclose a second front side conductive pattern coupled to the second front side power rail through the further front side metal layer. This allows more flexibility in terms of designing and optimizing the orientation and size of the rails and metal lines connecting them, as compared to using a single metal layer.
Do_757 further teaches the back side metal layer (Fig.4, element #PWL1) further comprises: a first back side conductive pattern (Fig.4, element #PWL1 on the right side of the figure) coupled to the first back side power rail (Fig.4, element #PWL1 on the left side of the figure) through the further back side metal layer (Fig.4, the two elements #PWL1 are coupled through element PWL2), the first FTV couples the first front side conductive pattern to the first back side conductive pattern (Fig.4, element #TVI couples elements #VDDG to element PWL1 on the right side of the figure). Do_757 does not explicitly teaches and a second back side conductive pattern coupled to the second back side power rail through the further back side metal layer, and the second FTV couples the first front side conductive pattern to the first back side conductive pattern. Nevertheless, Fig.27 shows the second back side power rail (element #PWL1 on the right side of the figure) coupled to the further metal layer, element #PWL2. It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to use the same design as the one used for the first backside power rail, that includes a back side conductive pattern coupled to the back side power rail through the further back side metal layer and a second FTV coupling the front side conductive pattern to the back side conductive pattern. Using conductive patterns coupled through higher order metal layers allows more flexibility in terms of designing and optimizing the backside power distribution network as compared to using a single metal layer, and allows the distribution of power to multiple points across the area of the device, through the connections formed using the conductive patterns.
Regarding claim 11, Do_757 teaches the method of claims 1 and 10, as set forth in the obviousness rejection. Do_757 further teaches the method of claim 10, wherein the plurality of FTVs comprises: a plurality of first FTVs including the first FTV (Fig.25, each PGC cell has a first FTV, one cell has the first FTV), and a plurality of second FTVs including the second FTV (Fig.25, each PGC cell has a second FTV, one cell has the second FTV), the front side metal layer comprises: a plurality of first front side conductive patterns including the first front side conductive pattern (Fig.25, each PGC cell has a first front side conductive pattern, #VDDG), and a plurality of second front side conductive patterns including the second front side conductive pattern (Fig.25, each PGC cell has a second front side conductive pattern), the back side metal layer comprises: a plurality of first back side conductive patterns including the first back side conductive pattern (Fig.25, each PGC cell has a first backside conductive pattern, #PWL1), and a plurality of second back side conductive patterns including the second back side conductive pattern (Fig.25, each PGC cell in the fourth column to the left has a second backside side conductive pattern), each of a plurality of first FTV structures comprises (Fig.25, each PGC cell in the first column to the left and third column to the right has a first FTV structure): one first front side conductive pattern among the plurality of first front side conductive patterns, one first back side conductive pattern among the plurality of first back side conductive patterns (Fig.25, each PGC cell in the column to the left and third column to the right has a first FTV structure comprising one first front side conductive pattern, one first backside conductive structure, one first FTV, as showed in Fig.4), and one first FTV among the plurality of first FTVs that couples the one first front side conductive pattern and the one first back side conductive pattern (one cell is a first cell), each of a plurality of second FTV structures comprises: one second front side conductive pattern among the plurality of second front side conductive patterns, one second back side conductive pattern among the plurality of second back side conductive patterns (Fig.25, each PGC cell in the fourth column to the left has a second FTV structure comprising one second front side conductive pattern, one second backside conductive structure), and one second FTV among the plurality of second FTVs that couples the one second front side conductive pattern and the one second back side conductive pattern (the one second front side and back side conductive patterns do not have to be in the first cell since VVDD lines span over multiple cells, as suggested in Fig.24), and the plurality of first FTV structures and the plurality of second FTV structures are arranged alternatingly along a first axis along which the first and second front side power rails extend (Fig.25, the first FTV structures in the first column to the left and third column to the right alternate with the second FTV structures in the fourth column to the left as the sequence repeats in the horizontal direction).
Regarding claim 15, Do_757 teaches the method of claim 1, as set forth in the obviousness rejection. Do_757 further teaches the method of claim 1, wherein the first front side power rail (Fig.3, element #VDD, paragraph [0045], row 2) and the first back side power rail (Fig.4, element #PWL1 on the left side of the figure) extend along a first axis (Fig.3, first axis is in horizontal direction, the back side power rail extends in the horizontal direction based on the cross-sections shown in Fig.4 and 5), and the first FTV is a slot FTV elongated along the first axis (Fig.3, element #TVI is a slot FTV).
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Do_757, in view of disclosed prior art, Gerben Doornbos et al., (United States Patent Application Publication Number US 2021/0098361 A1) hereinafter referenced as Doornbos.
Regarding claim 3, Do_757 teaches the method of claim 1, as set forth in the obviousness rejection. Do_757 further teaches an N-type transistor comprises (Fig.23, element PGT_N, paragraph [0125], row 11): a first source/drain coupled to the first front side power rail, and a second source/drain coupled to the second front side power rail (Fig.23, the source and drain of the PGT_N are coupled to VVDD and VDD). Do_757 does not teach, wherein the at least one circuit comprises a footer circuit comprising the transistor which is an N- type transistor. Doornbos teaches wherein at least one circuit comprises a footer circuit comprising the transistor which is an N- type transistor (Fig.1, paragraph [0022], rows 3-9). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Doornbos and disclose wherein the at least one circuit comprises a footer circuit comprising the transistor which is an N- type transistor. As disclosed by Doornbos, a footer circuit helps reduce power consumption in an integrated circuit (paragraph [0021], rows 7-16).
Claims 5, 7, 8 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Do_757, in view of disclosed prior art, Do et al., (United States Patent Application Publication Number US 2022/0122970 A1), hereinafter referenced as Do_970.
Regarding claim 5, Do_757 teaches the method of claim 1, as set forth in the obviousness rejection. Do_757 further teaches the method of claim 1, wherein the first front side power rail and the second front side power rail extend along a first axis (Fig.3, the power rails they extend along horizontal axis).
Do_757 does not teach the front side metal layer further comprises: a first conductive pattern projecting from the first front side power rail along a second axis transverse to the first axis, and a second conductive pattern projecting from the second front side power rail along the second axis, the first FTV couples the first back side power rail to the first conductive pattern, and the second FTV couples the second back side power rail to the second conductive pattern. Do_970 teaches wherein the front side metal layer (Fig.11, layer M1) further comprises: a first conductive pattern projecting from the first front side power rail along a second axis transverse to the first axis (Fig.10, first front side power rail, element #M1_R1(VDD), has a conductive projection, element #EXP1 located to the left side of the figure projecting from it, along vertical direction) and a second conductive pattern projecting from the second front side power rail along the second axis (Fig.11, second conductive projection, element #EXP3 projecting from it second power rails in vertical direction), and the first FTV (Fig.8B, element #TVI) couples the first back side power rail (Fig.11B, element #LM1 in the middle of the figure) to the first conductive pattern (Fig.8B, element #TVI couples element #EXP element #LM1 in the middle of the figure, paragraph [0094], rows 6-10), the second FTV couples the second back side power rail to the second conductive pattern (paragraph [0111], rows 1-12). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Do_970 and disclose wherein the front side metal layer further comprises: a first conductive pattern projecting from the first front side power rail along a second axis transverse to the first axis, and a second conductive pattern projecting from the second front side power rail along the second axis, and the first FTV couples the first back side power rail to the first conductive pattern, the second FTV couples the second back side power rail to the second conductive pattern. As disclosed by Bo_970 the conductive pattern allows the through via to be stably connected to the power rails (paragraph [0181], rows 13-15).
Regarding claim 7, Do_757 teaches the method of claim 1, as set forth in the obviousness rejection, and the combination Do_757 and Do_970 teaches the method of claim 5, as set forth in the obviousness rejection. Do_970 further teaches the method of claim 5, wherein the first conductive pattern (Fig.11, element #EXP1) projects from the first front side power rail (Fig.11 projects from element #M1_R1(VDD)) along the second axis (Fig.11, second axis is vertical direction) toward the second front side power rail (Fig.11, element #M1_R3(VSS)), and the second conductive pattern (Fig.11, element #EXP3) projects from the second front side power rail (Fig.11, element #M1_R3(VSS)) along the second axis (Fig.11, second axis is vertical direction) toward the first front side power rail (Fig.11 projects from element #M1_R1(VDD)).
Regarding claim 8, Do_757 teaches the method of claim 1, as set forth in the obviousness rejection and the combination Do_757 and Do_970 teaches the method of claims 5 and 7, as set forth in the obviousness rejection. Do_757 further teaches the method of claim 7, wherein the front side metal layer further comprises: a third front side power rail extending along the first axis (Fig.10, rail at the bottom of the figure, corresponding to #VVDD rail of transistor PGT2, same as bottom #VVDD rail in Fig.9, extending along horizontal axis) and electrically connected to the second front side power rail (the top and bottom VVDD rails are connected through extended source/drain contacts, CAE), wherein, along the second axis, the first front side power rail is between the second and third front side power rails (Fig.10, fist power rail VDD is between the two VVDD rails along vertical direction).
Do_757 does not teach a third conductive pattern projecting from the third front side power rail along the second axis toward the first front side power rail, and a fourth conductive pattern projecting from the first front side power rail along the second axis toward the third front side power rail. Do_970 teaches a third conductive pattern (Fig.11, element #EXP2) projecting from the third front side power rail (Fig.11, bottom rail #M1_R2(VSS)) along the second axis toward the first front side power rail (Fig.11, element #EXP2 projects towards element #M1_R1(VDD) in vertical direction), and a fourth conductive pattern (Fig.10, element #EXP2 on the right side of the figure) projecting from the first front side power rail along the second axis toward the third front side power rail (Fig.11, element #EXP2 projects towards element #M1_R2(VSS) in vertical direction). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Do_970 and disclose a third conductive pattern projecting from the third front side power rail along the second axis toward the first front side power rail, and a fourth conductive pattern projecting from the first front side power rail along the second axis toward the third front side power rail. As disclosed by Do_970 the conductive patterns allow the through vias to be stably connected to the power rails (paragraph [0181], rows 1-15).
Similar to the same embodiment used in the rejection of claim 1, Do_757 teaches a third back side power rail extending along the first axis (element similar to element #PWL1 on the right side of the Fig.27A), and electrically connected to the second back side power rail (they are electrically connected through the corresponding front side power rail which are electrically connected). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to combine the teachings of Do_757 and disclose a third back side power rail connected to the second back side power rail. In this way both VDD and VVDD, can be provided through the back side of the substrate, which can be easily achieved using a circuit board coupled to the backside of the substrate, and eliminate the need for a front side power source, or long interconnects around the substrate. Furthermore, electrically connecting power rails that carry the same power/signal values helps maintain uniform values across the device.
Do_970 further teaches the back side metal layer further comprises: a third back side power rail and electrically connected to the second back side power rail (Fig.11, rail corresponding to element #EXP2, paragraph [0111], rows 11-14 has the same voltage as the second power rail so they are connected at the power source), extending along the first axis (From cross sections of Fig.6A -6D one can determine that buried power rails, elements #LM1 extend in the horizontal direction, parallel to front side rails), wherein, along the second axis, the first back side power rail is between the second and third back side power rails (Fig.7 and cross-sections of Fig.8A and 8B show the buried power rails below the frontside power rails), and the plurality of FTVs further comprises: a third FTV extending through the substrate, and coupling the third back side power rail to the third conductive pattern on the front side metal layer, and a fourth FTV extending through the substrate, and coupling the first back side power rail to the fourth conductive pattern on the front side metal layer (a through via corresponds to each conductive pattern and the vias are coupled to corresponding backside rails, paragraph [0111], rows 11-15). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Do_970 and disclose a third back side power rail extending along the first axis and electrically connected to the second back side power rail, wherein, along the second axis, the first back side power rail is between the second and third back side power rails, and the plurality of FTVs further comprises: a third FTV extending through the substrate, and coupling the third back side power rail to the third conductive pattern on the front side metal layer, and a fourth FTV extending through the substrate, and coupling the first back side power rail to the fourth conductive pattern on the front side metal layer. As disclosed by Bo_970, the conductive patterns allow the through vias to be stably connected to the power rails (paragraph [0181], rows 1-15). Furthermore, connecting the front and back side power rails through vias eliminates the need for a front side power source, and provides short interconnects which minimizes losses.
Regarding claim 14, Do_757 teaches the method of claim 1, as set forth in the obviousness rejection. Do_757 further teaches The method of claim 1, wherein the first front side power rail (Fig.3, element #VDD, paragraph [0045], row 2) and the second front side power rail (Fig.3, element #VVDD on the top side of the image, paragraph [0045], row 4) extend along a first axis (Fig.3, first axis is the horizontal axis), the front side metal layer further comprises: a third front side power rail extending along the first axis (Fig.10, rail at the bottom of the figure, corresponding to #VVDD rail of transistor PGT2, same as bottom #VVDD rail in Fig.9, extending along horizontal axis), wherein, along a second axis transverse to the first axis (Fig.3, second axis is the vertical axis), the first front side power rail is between the second and third front side power rails (Fig.10, fist power rail, element #VDD, is between the two VVDD rails in vertical direction).
Do_757 does not teach a first conductive pattern projecting from the first front side power rail along the second axis toward the second and third front side power rails, a second conductive pattern projecting from the second front side power rail along the second axis toward the first and third front side power rails, and a third conductive pattern projecting from the third front side power rail along the second axis toward the first and second front side power rails. Do_970 teaches a first conductive pattern projecting from the first front side power rail along the second axis (Fig.11, first front side power rail, #M1_R1(VDD), has a conductive pattern, element #EXP1, projecting from it, along vertical direction) toward the second and third front side power rails (Fig.11, second rail is element #M1_R2(VSS) and third rail is element #M1_T2(VSS)), a second conductive pattern projecting from the second front side power rail along the second axis toward the first and third front side power rails (Fig.11, element #EXP3), and a third conductive pattern projecting from the third front side power rail along the second axis toward the first and second front side power rails (Fig.11, element #EXP2). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Do_970 and disclose a first conductive pattern projecting from the first front side power rail along the second axis toward the second and third front side power rails, a second conductive pattern projecting from the second front side power rail along the second axis toward the first and third front side power rails, and a third conductive pattern projecting from the third front side power rail along the second axis toward the first and second front side power rails. As disclosed by Bo_970 the conductive patterns allow the through via to be stably connected to the power rails (paragraph [0181], rows 13-15).
Similar to the same embodiment used for claim 1, Do_757 teaches the back side metal layer (Fig.27A, element #PWL1) further comprises: a third back side power rail (element similar to element #PWL1 on the right side of the Fig.27A, corresponding the third front side VVDD rail). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to combine the teachings of Do_757 and disclose a third back side power rail. In this way both VDD and VVDD, can be provided through the back side of the substrate, which can be easily achieved using a circuit board coupled to the backside of the substrate, and eliminates the need for a front side power source, or long interconnects around the substrate.
Do_970 further teaches the back side metal layer further comprises: a third back side power rail (rail corresponding to EXP2, paragraph [0111], rows 11-14) extending along the first axis (From cross sections of Fig.6A -6D one can determine that buried power rails, elements #LM1 extend in the horizontal direction, parallel to front side rails), wherein, along the second axis, the first back side power rail is between the second and third back side power rails (Fig.7 and cross-sections of Fig.8A and 8B show the buried power rails below the frontside power rails), the first FTV couples the first conductive pattern to the first back side power rail, the second FTV couples the second conductive pattern to the second back side power rail, and the plurality of FTVs further comprises a third FTV coupling the third conductive pattern to the third back side power rail (Fig.11, a FTV corresponds to each conductive pattern and are coupled to corresponding backside rails, paragraph [0111], rows 11-15). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Do_970 and disclose a third back side power rail extending along the first axis, wherein, along the second axis, the first back side power rail is between the second and third back side power rails, the first FTV couples the first conductive pattern to the first back side power rail, the second FTV couples the second conductive pattern to the second back side power rail, and the plurality of FTVs further comprises a third FTV coupling the third conductive pattern to the third back side power rail. As disclosed by Bo_970, the conductive patterns allow the through vias to be stably connected to the power rails (paragraph [0181], rows 1-15). Furthermore, connecting the front side and back side power rails through vias eliminates the need for a front side power source, and provides short interconnects which minimizes losses.
Claims 12 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Do_757, in view of Frank Trang et al., (United States Patent Application Publication Number US 2020/0020779 A1) hereinafter referenced as Trang.
Regarding claim 12, Do_757 teaches the method of claim 1, as set forth in the obviousness rejection. Do_757 further teaches the method of claim 1, wherein the first front side power rail (Fig.3, element #VDD, paragraph [0045], row 2 same as element #VDD in Fig.10) and the second front side power rail (Fig.3, element #VVDD on the top side of the image, paragraph [0045], row 4, same as element #VVDD on the top side of Fig.10) extend along a first axis (extend along horizontal axis), the front side metal layer (Fig.10, element #M1L) further comprises: a third front side power rail extending along the first axis (Fig.10, rail at the bottom of the figure, corresponding to rail element #VVDD of transistor PGT2, same as bottom #VVDD rail in Fig.9, extending along horizontal axis), wherein, along a second axis transverse to the first axis (second axis is vertical axis), the first front side power rail is between the second and third front side power rails (Fig.10, fist power rail, element #VDD, is between the two VVDD rails in vertical direction). Do_757 teaches the second FTV couples the second front side power rail with the second backside power rail (Fig.27A, element #TV_S coupled element #VVDD to element #PWL1 on the right side of the figure) and therefore couples the second back side power rail with any conductive pattern connected to the second front side power rail.
Do_757 does not teach and a first conductive pattern extending along the second axis, and coupling the second and third front side power rail, and the second FTV couples the first conductive pattern to the second back side power rail. Trang teaches a first conductive pattern extending along the second axis (Fig.17A, element #640, extends along vertical direction), and coupling the second and third front side power rail (Fig.17A, top and bottom elements #631, paragraph [0095], rows 15-17). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Trang and disclose a first conductive pattern extending along the second axis, and coupling the second and third front side power rail. Connecting power rails that are set to carry the same power/signal values helps maintain uniform values across the device.
Regarding claim 13, Do_757 teaches the method of claim 1, as set forth in the obviousness rejection, and the combination of Do_757 and Trang teaches the method of claim 12, as set forth in the obviousness rejection. Do_757 teaches the first FTV (Fig.4, element #TVI, paragraph [0062], row 3) is coupled to the first front side power rail (Fig.4, element #VDD, paragraph [0045], row 2) and back side power rails (Fig.4, element #VVDD on the top side of the image, paragraph [0045], row 4) and therefore, the back side power rail will be coupled to any conductive pattern projecting from the front side power rail.
Do_757 does not teach the method of claim 12, wherein the front side metal layer further comprises: a second conductive pattern projecting from an end of the first front side power rail along the second axis toward the second and third front side power rails, and the first front side power rail extends along the first axis from the second conductive pattern away from the first conductive pattern. Trang teaches wherein the front side metal layer (Fig.17A, top metal layer in Fig.15A and 15B) further comprises: a second conductive pattern projecting from an end of the first front side power rail along the second axis toward the second and third front side power rails (Fig.17A, first front side power rail, element #621 has a projection pattern on the right end of the rail, towards the second and third rails, elements #631) and the first front side power rail extends along the first axis from the second conductive pattern away from the first conductive pattern (Fig.17A, element #621 extends in the horizontal direction, away from the right side). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Trang and disclose the front side metal layer further comprises: a second conductive pattern projecting from an end of the first front side power rail along the second axis toward the second and third front side power rails, and the first front side power rail extends along the first axis from the second conductive pattern away from the first conductive pattern. As disclosed by Trang, the conductive pattern can be used to connect the first rail with multiple semiconductor structures located in between the first and second and third rails, and can be manufactured using the same process steps as the ones used to make the rail, since it is part of the rail. Thus, it eliminates the need for other metal layers for connections, while expanding the reach of the rail. Furthermore, placing the conductive pattern at the end of the rail allows short connections between the rail and semiconductor structures located nearby.
Claims 19 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Do_970, in view of Yang et al., (United States Patent Application Publication Number US 2018/0151411 A1) hereinafter referenced as Yang.
Regarding claim 19, Do_970 teaches a method of manufacturing an integrated circuit (IC) device, the method comprising: fabricating at least one circuit over a substrate having opposite front and back sides (Fig.8A, shows a side view of a part of the circuit over the substrate, having a front side and a back side); fabricating a front side redistribution structure over the front side of the substrate (Fig.28, formed by elements #M1_R1 and M2_R2 and #M2 layers partially showed in Fig.8A), the front side redistribution structure comprising: first and second front side power rails coupled to the at least one circuit (Fig.28, first power rail is #M1_R1(VDD) second from the top, and second power rail is #M1_R2(VSS) third from the top), and a plurality of front side conductive patterns (Fig.11, elements #EXP1 and #EXP3); fabricating a plurality of feed through vias (FTVs) extending through the substrate and coupled correspondingly to the plurality of front side conductive patterns (Fig.28, vias inside elements #TCR1 and #TCR3, connected to #M1_R1(VDD) lines, and vias inside elements #TCR2, connected to #M1_R2(VSS) lines), and fabricating a back side redistribution structure over the back side of the substrate (Fig.8A, element #PDN, paragraph [0111], row 13), the back side redistribution structure comprising: a plurality of back side conductive patterns correspondingly coupled to the plurality of FTVs to obtain a plurality of FTV structures (Fig.8A, each via has a backside conductive pattern, elements #LM1 below the vias), wherein each FTV structure of the plurality of FTV structures comprises: a front side conductive pattern among the plurality of front side conductive patterns, a back side conductive pattern among the plurality of back side conductive patterns (each via has a backside conductive pattern, elements #LM1 below the vias and a front side conductive pattern formed by either #EXP1 or #EXP3) and among the plurality of FTVs, an FTV extending through the substrate, and coupling the front side conductive pattern and the back side conductive pattern (each via couples the corresponding front side and backside conductive patterns), the plurality of FTV structures comprises a first set of FTV structures (Fig.28, first set is formed by vias inside elements #TCR1 and #TCR3 connected to top #M1_R1(VDD) line and via inside element #TCR2 connected to second from the top #M1_R2(VSS) line) and a second set of FTV structures (Fig.28, second set is formed by vias inside elements #TCR1 and #TCR3 connected to third for the top #M1_R1(VDD) line and via inside element #TCR2 connected to forth from the top #M1_R2(VSS) line), the first and second front side power rails are arranged between the first set of FTV structures and the second set of FTV structures (Fig.28, first power rail is #M1_R1(VDD) second from the top, and second power rail is #M1_R2(VSS) third from the top are arranged between the set of FTV as defined above).
Do_970 does not teach the front side redistribution structure further comprises: at least one first conductive pattern electrically coupling one FTV structure in the first set and one FTV structure in the second set to the first front side power rail, and at least one second conductive pattern electrically coupling a further FTV structure in the first set and a further FTV structure in the second set to the second front side power rail. Yang teaches the front side redistribution structure further comprises conductive patterns electrically coupling vias to power rails (Fig.2A, element #240; note the structure shown in Fig.2A repeats itself vertically so one can define a first and second power rails and via sets similar to the ones define above and corresponding to Fig.28 of Do_970). Thus, the combination of Do_970 and Yang teaches the front side redistribution structure further comprises: at least one first conductive pattern electrically coupling one FTV structure in the first set and one FTV structure in the second set to the first front side power rail, and at least one second conductive pattern electrically coupling a further FTV structure in the first set and a further FTV structure in the second set to the second front side power rail. It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to combine the teachings of Yang with the teaching of Do_970 and disclose at least one first conductive pattern electrically coupling one FTV structure in the first set and one FTV structure in the second set to the first front side power rail, and at least one second conductive pattern electrically coupling a further FTV structure in the first set and a further FTV structure in the second set to the second front side power rail. As disclosed by Yang, this allows more via access points for the power to be supplied to the power rails, resulting in more electrical connections to different portions of the circuit and better electromigration performance (paragraph [0032]).
Regarding claim 20, the combination of Do_970 and Yang teaches the method of claim 19, as set forth in the anticipation rejection. Yang further teaches the method of claim 19, wherein the at least one first conductive pattern comprises multiple first conductive patterns (Fig.2A, formed by elements #220a, #220c and #220e), the at least one second conductive pattern comprises multiple second conductive patterns (Fig.2A, formed by elements #220b, #220d and #220f), and the multiple first conductive patterns and the multiple second conductive patterns are arranged alternatingly along a first axis along which the first and second front side power rails extend (Fig.2A, elements #220 are arranged alternatively along horizontal direction along which power rails #208a and #208b extend). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teaching of Yang and disclose wherein the at least one first conductive pattern comprises multiple first conductive patterns, the at least one second conductive pattern comprises multiple second conductive patterns, and the multiple first conductive patterns and the multiple second conductive patterns are arranged alternatingly along a first axis along which the first and second front side power rails extend. This provides uniform power distribution across the power rails and prevents while providing more via access points for the power to be supplied to the power rails, resulting in more electrical connections to different portions of the circuit and better electromigration performance (paragraph [0032]).
Allowable Subject Matter
Claims 6 and 9 are allowed if written in independent form. Claim 16 is allowed. Claims 17 and 18 are allowed as being dependent on claim 16.
The following is a statement of reasons for the indication of allowable subject matter.
Regarding claim 6, the cited prior art does not teach or fairly suggests, along with other claimed features: “the back side metal layer further comprises: a third conductive pattern projecting from the first back side power rail along the second axis, and a fourth conductive pattern projecting from the second back side power rail along the second axis”. Do_757 and Do_970 both teach a third conductive pattern projecting from the first back side power rail along the second axis and coupled to the first FTV (Do_757, Fig.4, element #PWL2 and Do_970, Fig.8B, element #LM2), but the conductive patterns are in different back side metal layers.
Regarding claim 9, the cited prior art does not teach or fairly suggests, along with other claimed features: “the transistor is between (i) the first and third conductive patterns on one side and (ii) the second and fourth conductive patterns on another side, and the first and third conductive patterns are between the transistor and the further transistor”. Do_970 teaches all the conductive patterns are on one side of the transistor (Fig.11).
Regarding claim 16, the cited prior art does not teach or fairly suggests, along with other claimed features: “the back side metal layer further comprises: a third conductive pattern projecting from the first back side power rail along the second axis and coupled to the first FTV”. Do_757 and Do_970 both teach a third conductive pattern projecting from the first back side power rail along the second axis and coupled to the first FTV (Do_757, Fig.4, element #PWL2 and Do_970, Fig.8B, element #LM2), but the conductive patterns are in different back side metal layers.
Conclusion
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/CRISTIAN A TIVARUS/Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899
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