DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of Group I, Species 1b in the reply filed on August 12, 2026 is acknowledged. The traversal is on the ground(s) that the species were not clearly identified using figures. This is not found persuasive because the defining features of each species were clearly identified in the restriction requirement, as well as the claims that recited features that were limited to a single disclosed embodiment. The species were identified as Species 1a which required a wet etching process to expose the third channel regions and Species 1b which required a dry etching process to expose the third channel regions. The species were not identified based on figures because the application does not provide figures that show wet etching versus dry etching to expose the third channel regions. Figures 16A-16B, 20A-20B, and 21A-21B each show an etching process 143 which is described as only as a dry etching process, therefore the figures identified in the response do not disclose different species as related to the claims as originally presented. Since the elected figures 21A-21B show the dry etching process 143 to expose the third channel regions, this is taken as election of Species 1b.
The requirement is still deemed proper and is therefore made FINAL.
Claims 10, and 18-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected Group and Species, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on August 12, 2026.
Response to Amendment
This Office Action is in response to Applicant's amendments filed August 12, 2026. Claim 13 has been amended. Claims 21-25 have been added. Claims 10-11, and 18-20 have been canceled. Currently, claims 1-9, 12-17, and 21-25 are pending.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the passivation layer recited in claims 6, 16, and 24 must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-5, and 13-15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lin et al. (US 20210126113 A1) herein after “Lin”.
Regarding claim 1, Figs. 4A-13B of Lin disclose a method of forming a semiconductor device (Fig. 1, semiconductor device 100, ¶ [0021]), the method comprising:
forming a first fin (Fig. 4A, fins 105, ¶ [0021]), a second fin (105), and a third fin (105) that protrude above a substrate (Fig. 4A, substrate 201, ¶ [0024]), wherein the third fin (105) is between the first fin (105) and the second fin (105);
forming first channel regions (Fig. 7B, nanostructures 701, ¶ [0072]), second channel regions (701), and third channel regions (701) over the first fin (105), the second fin (105), and the third fin (105), respectively;
forming a dummy gate structure (Fig. 3A, dummy gate electrode 303, dummy gate dielectric 211, ¶ [0035]) over the first fin (105), the second fin (105), and the third fin (105) and around the first channel regions (701), the second channel regions (701), and the third channel regions (701);
forming an interlayer dielectric (ILD) layer (Fig. 6A, contact etch stop layer 601, ¶ [0068]) around the dummy gate structure (303, 211);
replacing the dummy gate structure (303, 211) with a gate structure (Fig. 8B, gate electrodes 107, gate dielectric 703, ¶ [0072]) (Figs. 7A-8B, “removing the dummy gate electrode 303 and the dummy gate dielectric 211”, “the formation of a gate dielectric 703 over the nanostructures 701”, ¶ [0072], “Once the gate dielectric 703 has been formed, the gate electrodes 107 are formed to surround the nanostructures 701”, ¶ [0081]);
after replacing the dummy gate structure (303, 211), forming a first dielectric plug (Fig. 10B, cut-metal gate structures 109, ¶ [0021]) in the gate structure (107, 703) between the first fin (105) and the third fin (105) and forming a second dielectric plug (109) in the gate structure (107, 703) between the third fin (105) and the second fin (105),
wherein the first dielectric plug (109) and the second dielectric plug (109) separate the gate structure (107, 703) into a plurality of segments; and
after forming the first dielectric plug (109) and the second dielectric plug (109), replacing a first segment of the gate structure (107, 703) disposed between the first dielectric plug (109) and the second dielectric plug (109) with an isolation structure (Fig. 13B, CPODE structure 111, ¶ [0099]).
Regarding claim 2, Figs. 4A-13B of Lin disclose the method of claim 1 as applied above, and Figs. 7A-8B of Lin further disclose wherein replacing the dummy gate structure (303, 211) comprises:
removing the dummy gate structure (303, 211) to form a gate trench in the ILD layer (601);
forming a gate dielectric material (703) in the gate trench around the first channel regions (701), the second channel regions (701), and the third channel regions (701); and
filling the gate trench with a gate electrode material (107).
Regarding claim 3, Figs. 4A-13B of Lin disclose the method of claim 1 as applied above, and Figs. 9A-10B of Lin further disclose wherein forming the first dielectric plug (109) and the second dielectric plug (109) comprises:
forming a first opening (Fig. 9B, second openings 901, ¶ [0090]) in the gate structure (107, 703) between the first fin (105) and the third fin (105);
forming a second opening (901) in the gate structure (107, 703) between the third fin (105) and the second fin (105), wherein the first opening (901) and the second opening (901) extend vertically through the gate structure (107, 703), wherein the first opening (901) and the second opening (901) extend laterally beyond opposing sidewalls of the gate structure (107, 703); and
filling the first opening (901) and the second opening (901) with a dielectric material (Fig. 10B, “Once the second openings 901 have been formed, the cut-metal gate structures 109 are formed by initially depositing a dielectric material to fill and overfill the second openings 901”, ¶ [0092]).
Regarding claim 4, Figs. 4A-13B of Lin disclose the method of claim 1 as applied above, and Figs. 11A-11B of Lin further disclose wherein replacing the first segment of the gate structure (107, 703) comprises:
performing one or more etching processes (“the etching process used to form the third opening 1003”, ¶ [0096]) to remove the first segment of the gate structure (107, 703) and form a recess (Fig. 11B, third opening 1003, ¶ [0094]) in the gate structure (107, 703) between the first dielectric plug (109) and the second dielectric plug (109), wherein the recess (1003) exposes the third channel regions (701);
after performing the one or more etching processes, performing a multi-step etching process to remove the third channel regions (701) (“a further etching process may be used to remove the materials of the nanostructures 701 and to form the recess within the fin 105. According to some embodiments, an etching process such as a wet etch, a dry etch, combinations”, ¶ [0098]); and
after performing the multi-step etching process, filling the recess (1003) with a dielectric material (“The CPODE structure 111 may be formed by depositing a dielectric material to fill and/or overfill the third opening 1003”, ¶ [0099]).
Regarding claim 5, Figs. 11A-11B of Lin disclose the method of claim 4 as applied above, and Figs. 11A-11B of Lin further disclose wherein the recess (1003) is formed to expose a first sidewall of the first dielectric plug (109), a second sidewall of the second dielectric plug (109), a third sidewall of a first gate spacer (Fig. 11A, top spacers 309, ¶ [0044]), and a fourth sidewall of a second gate spacer (309), wherein the first gate spacer (309) and the second gate spacer (309) extend along opposing sidewalls of the gate structure (107, 703).
Regarding claim 13, Figs. 4A-13B of Lin disclose a method of forming a semiconductor device (100), the method comprising:
forming a dummy gate structure (303, 211) over a fin (105) and around channel regions (701) disposed over the fin (105), wherein the fin (105) protrudes above a substrate (201);
forming an interlayer dielectric (ILD) layer (601) over the fin around the dummy gate structure (303, 211);
replacing the dummy gate structure (303, 211) with a gate structure (107, 703);
forming a first dielectric plug (109) and a second dielectric plug (109) in the gate structure (107, 703) on opposing sides of the fin, wherein the first dielectric plug (109) and the second dielectric plug (109) separate the gate structure (107, 703) into a plurality of segments that are spaced apart from each other;
removing a segment of the gate structure (107, 703) interposed between the first dielectric plug (109) and the second dielectric plug (109) to form a recess (1003) in the gate structure (107, 703), wherein the recess (1003) exposes the channel regions (701);
removing the exposed channel regions (701) by performing a multi-step etching process (“a further etching process may be used to remove the materials of the nanostructures 701 and to form the recess within the fin 105. According to some embodiments, an etching process such as a wet etch, a dry etch, combinations”, ¶ [0098]); and
after removing the exposed channel regions (701), filling the recess (1003) with a dielectric material (111).
Regarding claim 14, Figs. 4A-13B of Lin disclose the method of claim 13 as applied above, and Figs. 11A-11B of Lin further disclose wherein removing the segment of the gate structure (107, 703) comprises performing a wet etching process (“the etching process used to form the third opening 1003 may be an isotropic etching process (e.g., a wet etching process)”, ¶ [0096]).
Regarding claim 15, Figs. 11A-11B of Lin disclose the method of claim 14 as applied above, and Figs. 11A-11B of Lin further disclose wherein removing the segment of the gate structure (107, 703) further comprises performing a dry etching process after performing the wet etching process (“a dry etch… may be used to remove the material of the gate dielectric 703”, ¶ [0097]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 6, and 8-9 are rejected under 35 U.S.C. 103 as being unpatentable over Lin (US 20210126113 A1) in view of Huang et al. (US 20210336033 A1) herein after “Huang” and Jang et al. (US 20200135472 A1) herein after “Jang”.
Regarding claim 6, Figs. 11A-11B of Lin disclose the method of claim 4 as applied above, and Figs. 11A-11B of Lin further disclose performing the multi-step etching process (“a further etching process may be used to remove the materials of the nanostructures 701 and to form the recess within the fin 105. According to some embodiments, an etching process such as a wet etch, a dry etch, combinations”, ¶ [0098]) comprises:
performing an anisotropic etching process to remove at least portions of the third channel regions (“other suitable etching process including anisotropic etching processes (e.g., a dry etching processes or reactive ion etching (RIE) processes)”, “a further etching process may be used to remove the materials of the nanostructures 701”, ¶ [0096-0098]).
Lin fails to disclose forming a passivation layer along sidewalls of the recess, along a bottom of the recess, and around the third channel regions;
performing a first anisotropic etching process to remove the passivation layer from the bottom of the recess and from the third channel regions, wherein the passivation layer remains along the sidewalls of the recess after performing the first anisotropic etching process; and
after performing the first anisotropic etching process, performing a second anisotropic etching, wherein a first gas source used in the first anisotropic etching process is different from a second gas source used in the second anisotropic etching process.
In the similar field of endeavor of IC manufacturing processes, Fig. 10B of Huang discloses forming a passivation layer (Fig. 10B, passivation layer 342, ¶ [0039]) along sidewalls of the recess (Fig. 10B, gate trenches 275, ¶ [0026]), along a bottom of the recess (275), and around the third channel regions (Fig. 10B, channel layers 215, ¶ [0024]) (“the passivation layer 342 wraps around (surrounds) each of the channel layers 215”, ¶ [0039]),
a first etching process to remove the passivation layer (342) from the bottom of the recess (275) and from the third channel regions (215).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the method of Lin with the passivation layer around the channel regions as disclosed by Huang, to protect the layers during subsequent etching steps (see Huang, ¶ [0039]).
Huang fails to disclose performing a first anisotropic etching process, wherein the passivation layer remains along the sidewalls of the recess after performing the first anisotropic etching process; and
after performing the first anisotropic etching process, performing a second anisotropic etching process, wherein a first gas source used in the first anisotropic etching process is different from a second gas source used in the second anisotropic etching process.
In the similar field of endeavor of semiconductor manufacturing, Figs. 13-18 of Jang disclose performing a first anisotropic etching process, wherein the passivation layer (Fig. 14, dielectric layer 76, ¶ [0036]) remains along the sidewalls of the recess after performing the first anisotropic etching process (“the bottom portion of dielectric layer 76 at the bottom of trench 74 is removed in an anisotropic etching/bombardment process”, ¶ [0037]); and
after performing the first anisotropic etching process, performing a second anisotropic etching process (Fig. 16, “another etching process is performed to extend trench 74 deeper into gate electrode 56”, ¶ [0038]), wherein a first gas source used in the first anisotropic etching process (“In accordance with some embodiments, a carbon-and-fluorine gas (such as C.sub.4F.sub.6) is used to etch the bottom portion of dielectric layer 76”, ¶ [0037]) is different from a second gas source used in the second anisotropic etching process (“The etching is performed using an appropriate etching gas…, for example, using oxygen (O.sub.2)”, ¶ [0038]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the method of Lin to include the etching steps as disclosed by Jang, to achieve more uniform removal (see Jang, ¶ [0043-0044]).
Regarding claim 8, Lin, Huang and Jang together disclose the method of claim 6 as applied above, but Lin and Huang fail to disclose wherein before filling the recess, the multi-step etching process is performed multiple times.
In the similar field of endeavor of semiconductor manufacturing, Figs. 13-18 and 20A of Jang disclose wherein before filling the recess (Fig. 20A, “The formation of dielectric (isolation) region 82 may include depositing a dielectric material into trench 74”, ¶ [0049]), the multi-step etching process is performed multiple times (Figs. 14-16, “the etching of gate electrode 56 includes a plurality of deposition-etching cycles, each including a dielectric-deposition process, a dielectric breaking process, an etching process to extend trench 74 down”, ¶ [0039]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the method of Lin to include the etching steps as disclosed by Jang, to achieve more uniform removal (see Jang, ¶ [0043-0044]).
Regarding claim 9, Lin, Huang and Jang together disclose the method of claim 6 as applied above, and Figs. 11A-11B of Lin further disclose wherein performing the one or more etching processes comprises performing a wet etching process (“another etching process is performed to remove the materials of the gate dielectric 703 within the third opening 1003 and to expose the nanostructures 701”, “a wet etch… may be used to remove the material of the gate dielectric 703”, ¶ [0097]).
Claims 7, 12, 16-17, and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Lin (US 20210126113 A1), Huang (US 20210336033 A1) and Jang (US 20200135472 A1) in further view of Wang et al. (US 20200006075 A1) herein after “Wang”.
Regarding claim 7, Lin, Huang and Jang together disclose the method of claim 6 as applied above, but Lin and Huang fail explicitly to disclose wherein the first anisotropic etching process and the second anisotropic etching process are plasma etching processes.
In the similar field of endeavor of semiconductor manufacturing, Figs. 13-18 of Jang disclose wherein the first anisotropic etching process (“In accordance with some embodiments, a carbon-and-fluorine gas (such as C.sub.4F.sub.6) is used to etch the bottom portion of dielectric layer 76”, ¶ [0037]) and the second anisotropic etching (“The etching is performed using an appropriate etching gas…, for example, using oxygen (O.sub.2)”, ¶ [0038]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the method of Lin to include the etching steps as disclosed by Jang, to achieve more uniform removal (see Jang, ¶ [0043-0044]).
Jang fails to explicitly disclose that the etching processes are plasma etching.
In the similar field of endeavor of semiconductor device manufacturing, Fig. 3A of Wang discloses wherein the etching processes are plasma etching (“the second etching step is an anisotropic etching, such as… plasma etching”, ¶ [0045]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the method of Lin to include the plasma process as disclosed by Wang, to obtain different selectivity in the etching processes (see Wang, ¶ [0045]) and/or because the known technique of plasma dry etching was recognized as part of ordinary capabilities of one skilled in the art. See KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Regarding claim 12, Lin, Huang and Jang together disclose the method of claim 9 as applied above, and Figs. 11A-12B of Lin further disclose wherein the wet etching process removes an upper portion of the first segment of the gate structure (107, 703) (“etch the excess dielectric material, edge portions of the cut-metal gate structures 109, the gate cap 801, and the gate electrode 107”, ¶ [0096]), and a lower portion of the first segment of the gate structure (107, 703) remains after the wet etching process, wherein performing the one or more etching processes further comprises, after performing the wet etching process, performing an etching process to remove the lower portion of the first segment of the gate structure (107, 703) and to expose the third channel regions (701) (Fig. 12A-12B, “another etching process is performed to remove the materials of the gate dielectric 703 within the third opening 1003 and to expose the nanostructures 701”, ¶ [0097]).
Lin, Huang and Jang fail to explicitly disclose that the etching processes are plasma etching.
In the similar field of endeavor of semiconductor device manufacturing, Fig. 3A of Wang discloses wherein the etching processes are plasma etching (“the second etching step is an anisotropic etching, such as… plasma etching”, ¶ [0045]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the method of Lin to include the plasma process as disclosed by Wang, to obtain different selectivity in the etching processes (see Wang, ¶ [0045]) and/or because the known technique of plasma dry etching was recognized as part of ordinary capabilities of one skilled in the art. See KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Regarding claim 16, Figs. 4A-13B of Lin disclose the method of claim 13 as applied above, and Figs. 11A-11B of Lin further disclose performing the multi-step etching process (“a further etching process may be used to remove the materials of the nanostructures 701 and to form the recess within the fin 105. According to some embodiments, an etching process such as a wet etch, a dry etch, combinations”, ¶ [0098]) comprises:
performing a plasma etching process to remove at least portions of third channel regions (“other suitable etching process including anisotropic etching processes (e.g., a dry etching processes or reactive ion etching (RIE) processes)”, “a further etching process may be used to remove the materials of the nanostructures 701”, ¶ [0096-0098]).
Lin fails to disclose forming a passivation layer along sidewalls of the recess, along a bottom of the recess, and along surface the channel regions;
performing a first plasma etching process to remove the passivation layer from the bottom of the recess and from the channel regions, wherein the passivation layer along the sidewalls of the recess remains after performing the first plasma etching process; and
after performing the first plasma etching process, performing a second plasma etching, wherein a first gas source used in the first plasma etching process is different from a second gas source used in the second plasma etching process.
In the similar field of endeavor of IC manufacturing processes, Fig. 10B of Huang discloses forming a passivation layer (342) along sidewalls of the recess (275), along a bottom of the recess (275), and along surfaces the channel regions (215) (“the passivation layer 342 wraps around (surrounds) each of the channel layers 215”, ¶ [0039]),
a first etching process to remove the passivation layer (342) from the bottom of the recess (275) and from the surfaces of the channel regions (215).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the method of Lin with the passivation layer around the channel regions as disclosed by Huang, to protect the layers during subsequent etching steps (see Huang, ¶ [0039]).
Huang fails to disclose performing a first plasma etching process, wherein the passivation layer along the sidewalls of the recess remains after performing the first plasma etching process; and
after performing the first plasma etching process, performing a second plasma etching, wherein a first gas source used in the first plasma etching process is different from a second gas source used in the second plasma etching process.
In the similar field of endeavor of semiconductor manufacturing, Figs. 13-18 of Jang disclose performing a first etching process, wherein the passivation layer (76) remains along the sidewalls of the recess after performing the first etching process (“the bottom portion of dielectric layer 76 at the bottom of trench 74 is removed in an anisotropic etching/bombardment process”, ¶ [0037]); and
after performing the first etching process, performing a second etching process (Fig. 16, “another etching process is performed to extend trench 74 deeper into gate electrode 56”, ¶ [0038]), wherein a first gas source used in the first etching process (“In accordance with some embodiments, a carbon-and-fluorine gas (such as C.sub.4F.sub.6) is used to etch the bottom portion of dielectric layer 76”, ¶ [0037]) is different from a second gas source used in the second etching process (“The etching is performed using an appropriate etching gas…, for example, using oxygen (O.sub.2)”, ¶ [0038]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the method of Lin to include the etching steps as disclosed by Jang, to achieve more uniform removal (see Jang, ¶ [0043-0044]).
Jang fails to disclose plasma etching processes are used.
In the similar field of endeavor of semiconductor device manufacturing, Fig. 3A of Wang discloses plasma etching processes are used (“the second etching step is an anisotropic etching, such as… plasma etching”, ¶ [0045]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the method of Lin to include the plasma dry etching as disclosed by Wang, to obtain different selectivity in the etching processes (see Wang, ¶ [0045]) and/or because the known technique of plasma dry etching was recognized as part of ordinary capabilities of one skilled in the art. See KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Regarding claim 17, Lin, Huang, Jang and Wang together disclose the method of claim 16 as applied above, but Lin, Huang and Wang fail to disclose wherein the multi-step etching process is performed multiple times before filling the recess.
In the similar field of endeavor of semiconductor manufacturing, Figs. 13-18 and 20A of Jang disclose wherein the multi-step etching process is performed multiple times (Figs. 14-16, “the etching of gate electrode 56 includes a plurality of deposition-etching cycles, each including a dielectric-deposition process, a dielectric breaking process, an etching process to extend trench 74 down”, ¶ [0039]) before filling the recess (Fig. 20A, “The formation of dielectric (isolation) region 82 may include depositing a dielectric material into trench 74”, ¶ [0049]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the method of Lin to include the etching steps as disclosed by Jang, to achieve more uniform removal (see Jang, ¶ [0043-0044]).
Regarding claim 21, Lin, Huang, Jang and Wang together disclose the method of claim 12 as applied above, and Figs. 11A-11B of Lin further disclose comprising, after forming the dummy gate structure (303) and before forming the ILD layer (601), forming gate spacers (309) along opposing sidewalls of the dummy gate structure (303), wherein the ILD layer (601) is formed around the gate spacers (309) and the dummy gate structure (303), wherein after performing the wet etching process and before performing the etching process, the lower portion of the first segment of the gate structure (107, 703) remains between the gate spacers (309) and around the third channel regions (701).
Lin, Huang and Jang fail to disclose plasma etching processes are used.
In the similar field of endeavor of semiconductor device manufacturing, Fig. 3A of Wang discloses plasma etching processes are used (“the second etching step is an anisotropic etching, such as… plasma etching”, ¶ [0045]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the method of Lin to include the plasma dry etching as disclosed by Wang, to obtain different selectivity in the etching processes (see Wang, ¶ [0045]) and/or because the known technique of plasma dry etching was recognized as part of ordinary capabilities of one skilled in the art. See KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Claim 22 is rejected under 35 U.S.C. 103 as being unpatentable over Lin (US 20210126113 A1), Huang (US 20210336033 A1), Jang (US 20200135472 A1) and Wang (US 20200006075 A1) in further view of Ng et al. (US 20210183855 A1) herein after “Ng”.
Regarding claim 22, Lin, Huang, Jang and Wang together disclose the method of claim 12 as applied above, and Figs. 11A-12B of Lin further disclose performing the multi-step etching process (“a further etching process may be used to remove the materials of the nanostructures 701 and to form the recess within the fin 105. According to some embodiments, an etching process such as a wet etch, a dry etch, combinations”, ¶ [0098]) removes a portion of the fin (105).
The combination fails to disclose the etching process further removes the fin and extends the recess into the substrate, wherein after performing the multi-step etching process, a center region of the bottom of the recess is flat, and peripheral regions of the bottom of the recess comprise protrusions that extend deeper into the substrate than the center region of the bottom of the recess.
In the similar field of endeavor of multi-gate devices, Figs. 1 and 7-2 of Ng disclose the etching process further removes the fin (Fig. 1, lower fin element 103, ¶ [0020]) and extends the recess into the substrate (Fig. 7-2, substrate 102, ¶ [0018]), wherein after performing the multi-step etching process, a center region of the bottom of the recess is flat (Fig. 7-2, center portion of isolation feature 146), and peripheral regions of the bottom of the recess comprise protrusions (Fig. 7-2, protrusions of isolation feature 146 into the substrate 102) that extend deeper into the substrate (102) than the center region of the bottom of the recess.
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to substitute the recess of Lin for the recess with protrusions into the substrate as disclosed by Ng. The claimed recess structure was known in the prior art and one skilled in the art could have combined the structure of Lin with that of Ng as claimed with no change in their respective functions, and the combination would have yielded the predictable result of isolating adjacent gate structures. See KSR International Co. V. Teleflex Inc., 82 USPQ2d 1385 (2007).
Claim 23 is rejected under 35 U.S.C. 103 as being unpatentable over Lin (US 20210126113 A1) in view of Wang (US 20200006075 A1).
Regarding claim 23, Figs. 4A-13B of Lin disclose a method of forming a semiconductor device (100), the method comprising:
forming a dummy gate structure (303) over a fin (105) and around channel regions (701) disposed over the fin (105), wherein the fin (105) protrudes above a substrate (201);
forming an interlayer dielectric (ILD) layer (601) over the fin (105) around the dummy gate structure (303);
replacing the dummy gate structure (303) with a replacement gate structure (107, 703);
forming a first dielectric plug (109) and a second dielectric plug (109) on opposing sides of the fin (105), wherein the first dielectric plug (109) and the second dielectric plug (109) are embedded in the replacement gate structure (107, 703) and separate the replacement gate structure (107, 703) into a plurality of segments that are spaced apart from each other;
removing a segment of the replacement gate structure (107, 703) interposed between the first dielectric plug (109) and the second dielectric plug (109) to form a recess (1003) in the replacement gate structure (107, 703), wherein the recess (1003) exposes the channel regions (701), wherein removing the segment of the replacement gate structure (107, 703) comprises:
performing a wet etching process to remove an upper portion of the segment of the replacement gate structure (107, 703) (“the etching process used to form the third opening 1003 may be an isotropic etching process (e.g., a wet etching process)”, ¶ [0096]); and
after performing the wet etching process, performing an etching process to remove a remaining portion of the segment of the replacement gate structure (“a dry etch, combinations, or the like may be used to remove the material of the gate dielectric 703”, ¶ [0097]);
removing the exposed channel regions (701) by performing a multi-step etching process (“a further etching process may be used to remove the materials of the nanostructures 701 and to form the recess within the fin 105. According to some embodiments, an etching process such as a wet etch, a dry etch, combinations”, ¶ [0098]); and
after removing the exposed channel regions (701), filling the recess (1003) with a dielectric material (111).
Lin fails to disclose a plasma etching process is used.
In the similar field of endeavor of semiconductor device manufacturing, Fig. 3A of Wang discloses a plasma etching process is used (“the second etching step is an anisotropic etching, such as… plasma etching”, ¶ [0045]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the method of Lin to include the plasma dry etching as disclosed by Wang, to obtain different selectivity in the etching processes (see Wang, ¶ [0045]) and/or because the known technique of plasma dry etching was recognized as part of ordinary capabilities of one skilled in the art. See KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Claims 24 is rejected under 35 U.S.C. 103 as being unpatentable over Lin (US 20210126113 A1) and Wang (US 20200006075 A1) in further view of Huang (US 20210336033 A1) and Jang (US 20200135472 A1).
Regarding claim 24, Lin and Wang together disclose the method of claim 23 as applied above, and Figs. 11A-11B of Lin further disclose performing the multi-step etching process (“a further etching process may be used to remove the materials of the nanostructures 701 and to form the recess within the fin 105. According to some embodiments, an etching process such as a wet etch, a dry etch, combinations”, ¶ [0098]) comprises:
performing an etching process to remove the channel regions (“other suitable etching process including anisotropic etching processes (e.g., a dry etching processes or reactive ion etching (RIE) processes)”, “a further etching process may be used to remove the materials of the nanostructures 701”, ¶ [0096-0098]).
Lin fails to disclose the etching processes are plasma etching processes;
lining a passivation layer along sidewalls of the recess, along a bottom of the recess, and along surface the channel regions;
performing a second plasma etching process to remove the passivation layer from the bottom of the recess and from the surfaces channel regions, wherein after performing the second plasma etching process the passivation layer remains along the sidewalls of the recess; and
after performing the second plasma etching process, performing a third plasma etching process different from the second plasma etching process.
In the similar field of endeavor of semiconductor device manufacturing, Fig. 3A of Wang discloses plasma etching processes are used (“the second etching step is an anisotropic etching, such as… plasma etching”, ¶ [0045]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the method of Lin to include the plasma dry etching as disclosed by Wang, to obtain different selectivity in the etching processes (see Wang, ¶ [0045]) and/or because the known technique of plasma dry etching was recognized as part of ordinary capabilities of one skilled in the art. See KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Wang fails to disclose lining a passivation layer along sidewalls of the recess, along a bottom of the recess, and along surface the channel regions;
performing a second etching process to remove the passivation layer from the bottom of the recess and from the surfaces channel regions, wherein after performing the second etching process the passivation layer remains along the sidewalls of the recess; and
after performing the second etching process, performing a third etching process different from the second etching.
In the similar field of endeavor of IC manufacturing processes, Fig. 10B of Huang discloses forming a passivation layer (342) along sidewalls of the recess (275), along a bottom of the recess (275), and along surfaces the channel regions (215) (“the passivation layer 342 wraps around (surrounds) each of the channel layers 215”, ¶ [0039]),
a second etching process to remove the passivation layer (342) from the bottom of the recess (275) and from the surfaces of the channel regions (215).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the method of Lin with the passivation layer around the channel regions as disclosed by Huang, to protect the layers during subsequent etching steps (see Huang, ¶ [0039]).
Huang fails to disclose performing a second etching process, wherein the passivation layer along the sidewalls of the recess remains after performing the second etching process; and
after performing the second etching process, performing a third etching different from the second plasma etching process.
In the similar field of endeavor of semiconductor manufacturing, Figs. 13-18 of Jang disclose performing a second etching process, wherein the passivation layer (76) remains along the sidewalls of the recess after performing the first anisotropic etching process (“the bottom portion of dielectric layer 76 at the bottom of trench 74 is removed in an anisotropic etching/bombardment process”, ¶ [0037]); and
after performing the second etching process, performing a third etching process (Fig. 16, “another etching process is performed to extend trench 74 deeper into gate electrode 56”, ¶ [0038]) is different from the second etching process (“In accordance with some embodiments, a carbon-and-fluorine gas (such as C.sub.4F.sub.6) is used to etch the bottom portion of dielectric layer 76”, ¶ [0037], “The etching is performed using an appropriate etching gas…, for example, using oxygen (O.sub.2)”, ¶ [0038]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the method of Lin to include the etching steps as disclosed by Jang, to achieve more uniform removal (see Jang, ¶ [0043-0044]).
Claims 25 is rejected under 35 U.S.C. 103 as being unpatentable over Lin (US 20210126113 A1), Wang (US 20200006075 A1), Huang (US 20210336033 A1) and Jang (US 20200135472 A1) in further view of Ng (US 20210183855 A1).
Regarding claim 25, Lin, Wang, Huang and Jang together disclose the limitations of claim 24 as applied above, and Figs. 11A-12B of Lin further disclose performing the multi-step etching process (“a further etching process may be used to remove the materials of the nanostructures 701 and to form the recess within the fin 105. According to some embodiments, an etching process such as a wet etch, a dry etch, combinations”, ¶ [0098]) removes a portion of the fin (105).
The combination fails to disclose wherein performing the multi-step etching process further removes the fin and extends the recess into the substrate, wherein after performing the multi-step etching process, the bottom of the recess comprises a flat center region, a first protrusion, and a second protrusion, wherein the flat center region is interposed laterally between the first protrusion and the second protrusion, wherein the first protrusion and the second protrusion extend deeper into the substrate than the flat center region of the bottom of the recess.
In the similar field of endeavor of multi-gate devices, Figs. 1 and 7-2 of Ng disclose the etching process further removes the fin (Fig. 1, lower fin element 103, ¶ [0020]) and extends the recess into the substrate (Fig. 7-2, substrate 102, ¶ [0018]), wherein after performing the multi-step etching process, the bottom of the recess comprises a flat center region (Fig. 7-2, center portion of isolation feature 146), a first protrusion, and a second protrusion (Fig. 7-2, protrusions of isolation feature 146 into the substrate 102), wherein the flat center region is interposed laterally between the first protrusion and the second protrusion (shown in Fig. 7-2), wherein the first protrusion and the second protrusion extend deeper into the substrate (102) than the flat center region of the bottom of the recess (shown in Fig. 7-2).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to substitute the recess of Lin for the recess with protrusions into the substrate as disclosed by Ng. The claimed recess structure was known in the prior art and one skilled in the art could have combined the structure of Lin with that of Ng as claimed with no change in their respective functions, and the combination would have yielded the predictable result of isolating adjacent gate structures. See KSR International Co. V. Teleflex Inc., 82 USPQ2d 1385 (2007).
Conclusion
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/C.A.N./Examiner, Art Unit 2893
/YARA B GREEN/Supervisor Patent Examiner, Art Unit 2893
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