DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims of U.S. Patent No. 12,475,952. Although the claims at issue are not identical, they are not patentably distinct from each other because the limitations recited in claims 1-20 of the instant application are encompassed by claims of U.S. Patent No. 12,475,952.
Instant Application
Claim
U.S. Patent No. 12,475,952
Claim
1
1, 2
2
1, 2
3
3
4
4
5
5
6
6
7
7
8
8, 13
9
9
10
10
11
11
12
12
13
8, 13
14
14
15
15, 20
16
16
17
17
18
18
19
19
20
15, 20
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2 and 4 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Norman et al. (US 2021/0248094).
Regarding claim 1, Norman et al. discloses, as shown in Figures 2-3, a semiconductor device comprising:
a first level (202a-202c) comprising memory control circuits (memory controller), said memory control circuits comprising first transistors (QV, DRAM including transistor and capacitor, [0004],[0006]);
a second level (memory die 1) disposed on top of said first level, said second level comprising a first array of memory cells comprising second transistors (QV, DRAM including transistor and capacitor, [0004],[0006]);
a third level (memory die 2) disposed on top of said second level, said third level comprising a second array of memory cells comprising third transistors (QV, DRAM including transistor and capacitor, [0004],[0006]);
a fourth level (memory die 3) disposed on top of said third level, said fourth level comprising a third array of memory cells comprising fourth transistors (QV, DRAM including transistor and capacitor, [0004],[0006]),
wherein said second level is bonded (by micro bumps) to said first level,
wherein said memory control circuits comprise cache memory (Abstract, [0013], etc.), and
wherein said second array of memory cells comprise a plurality of independently controlled memory units (different memory dies 2); and
a plurality of refresh circuits for said memory units [0005]-[0006], [0057].
Regarding claim 2, Norman et al. discloses the second level comprising memory die 1 having the second transistor is aligned with the third level comprising memory die 2 having the third transistor.
Note that the term “self-aligned …, being processed following a same lithography step” is method recitation in a device claimed. “[E]ven though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process.” In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985).
Regarding claim 4, Norman et al. discloses memory cells each comprises a charge trap layer (ONO, [0006]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 3, 6 and 8-11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Norman et al. (US 2021/0248094, hereafter Norman et al.’094) in view of Norman et al. (US 2020/0326889, hereafter Norman et al.’889).
Regarding claim 3, Norman et al.’094 discloses the claimed invention including the device as explained in the above rejection. Norman et al.’094 does not disclose the device further comprising a plurality of redundancy memory cells. However, Norman et al.’889 discloses a device comprising a plurality of redundancy memory cells. Note [0058] and [0068] of Norman et al.’889. Therefore, it would have been obvious to one of ordinary skills in the art at the time the invention was made to form the device of Norman et al.’094 comprising a plurality of redundancy memory cells, such as taught by Norman et al.’889 in order to correct the error events.
Regarding claim 6, Norman et al.’094 discloses the claimed invention including the device as explained in the above rejection. Norman et al.’094 does not disclose the device further comprising a plurality of One Time Programmable (“OTP”) fuses. However, Norman et al.’889 discloses a device comprising a plurality of OTP fuses. Note [0058] and [0068] of Norman et al.’889. Therefore, it would have been obvious to one of ordinary skills in the art at the time the invention was made to form the device of Norman et al.’094 comprising a plurality of OTP, such as taught by Norman et al.’889 in order to correct the error events.
Regarding claim 8, Norman et al.’094 discloses, as shown in Figures 2-3, a semiconductor device comprising:
a first level (202a-202c) comprising memory control circuits (memory controller), said memory control circuits comprising first transistors (QV, DRAM including transistor and capacitor, [0004],[0006]);
a second level (memory die 1) disposed on top of said first level, said second level comprising a first array of memory cells comprising second transistors (QV, DRAM including transistor and capacitor, [0004],[0006]);
a third level (memory die 2) disposed on top of said second level, said third level comprising a second array of memory cells comprising third transistors (QV, DRAM including transistor and capacitor, [0004],[0006]);
a fourth level (memory die 3) disposed on top of said third level, said fourth level comprising a third array of memory cells comprising fourth transistors (QV, DRAM including transistor and capacitor, [0004],[0006]),
wherein said second level is bonded (by micro bumps) to said first level,
wherein said memory control circuits comprise cache memory (Abstract, [0013], etc.), and
wherein said second array of memory cells comprise a plurality of independently controlled memory units (different memory dies 2).
Norman et al.’094 does not disclose a plurality of One Time Programmable (“OTP”) fuses. However, Norman et al.’889 discloses a device comprising a plurality of OTP fuses. Note [0058] and [0068] of Norman et al. Therefore, it would have been obvious to one of ordinary skills in the art at the time the invention was made to form the device of Norman et al.’094 comprising a plurality of OTP, such as taught by Norman et al.’889 in order to correct the error events.
Regarding claim 9, Norman et al.’094 and Norman et al.’889 disclose the memory control circuits comprising a plurality of refresh circuits for said memory units [0005]-[0006], [0057].
Regarding claim 10, Norman et al.’094 and Norman et al.’889 disclose the plurality of independently controlled memory units comprises at least four memory units (arrays).
Regarding claim 11, Norman et al.’094 and Norman et al.’889 disclose the memory cells each comprises a charge trap layer (ONO, [0006]).
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Norman et al. (US 2021/0248094) in view of Tanzawa (US 2012/0273862).
Norman et al. discloses the claimed invention including the device as explained in the above rejection. Norman et al. does not disclose a transistor channel of at least one of the second transistors comprises polysilicon. However, Tanzawa disclose a transistor channel (118, 120) comprises polysilicon. Note Figure 1 and [0028] of Tanzawa. Therefore, it would have been obvious to one of ordinary skills in the art at the time the invention was made to form the transistor channel of Norman et al. comprising polysilicon, such as taught bv Tanzawa in order to have the desired conductivity.
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Norman et al. (US 2021/0248094) in view of Hwang et al. (US 2022/0139821).
Regarding claim 7, Norman et al. discloses the claimed invention including the device as explained in the above rejection. Norman et al. does not disclose the device further comprising a fifth level disposed on top of the fourth level, wherein the fifth level comprises single crystal silicon. However, Hwang et al. discloses a fifth level (100) comprising single crystal silicon on top of a fourth level (260). Note Figures 25-31 and [0062] of Hwang et al. Therefore, it would have been obvious to one of ordinary skills in the art at the time the invention was made to form the device of Norman et al. having a fifth level, such as taught by Hwang et al. in order to form a common source plate to perform the desired function.
Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Norman et al. (US 2021/0248094, hereafter Norman et al.’094) in view of Norman et al. (US 2020/0326889, hereafter Norman et al.’889) and further in view of Tanzawa (US 2012/0273862).
Norman et al.’094 and Norman et al.’889 disclose the claimed invention including the device as explained in the above rejection. Norman et al.’094 and Norman et al.’889 do not disclose a transistor channel of at least one of the second transistors comprises polysilicon. However, Tanzawa disclose a transistor channel (118, 120) comprises polysilicon. Note Figure 1 and [0028] of Tanzawa. Therefore, it would have been obvious to one of ordinary skills in the art at the time the invention was made to form the transistor channel of Norman et al.’094 and Norman et al.’889 comprising polysilicon, such as taught bv Tanzawa in order to have the desired conductivity.
Claim(s) 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Norman et al. (US 2021/0248094, hereafter Norman et al.’094) in view of Norman et al. (US 2020/0326889, hereafter Norman et al.’889) and further in view of Hwang et al. (US 2022/0139821).
Norman et al.’094 and Norman et al.’889 disclose the claimed invention including the device as explained in the above rejection. Norman et al.’094 and Norman et al.’889 do not disclose the device further comprising a fifth level disposed on top of the fourth level, wherein the fifth level comprises single crystal silicon. However, Hwang et al. discloses a fifth level (100) comprising single crystal silicon on top of a fourth level (260). Note Figures 25-31 and [] of Hwang et al. Therefore, it would have been obvious to one of ordinary skills in the art at the time the invention was made to form the device of Norman et al. having a fifth level, such as taught by Hwang et al. in order to form a common source plate to perform the desired function.
Claim(s) 15-17 and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Norman et al. (US 2021/0248094, hereafter Norman et al.’094) in view of Hwang et al. (US 2022/0139821) and further in view of Norman et al. (US 2020/0326889, hereafter Norman et al.’889).
Regarding claim 15, Norman et al.’094 discloses, as shown in Figures 2-3, a semiconductor device comprising:
a first level (202a-202c) comprising memory control circuits (memory controller), said memory control circuits comprising first transistors (QV, DRAM including transistor and capacitor, [0004],[0006]);
a second level (memory die 1) disposed on top of said first level, said second level comprising a first array of memory cells comprising second transistors (QV, DRAM including transistor and capacitor, [0004],[0006]);
a third level (memory die 2) disposed on top of said second level, said third level comprising a second array of memory cells comprising third transistors (QV, DRAM including transistor and capacitor, [0004],[0006]);
a fourth level (memory die 3) disposed on top of said third level, said fourth level comprising a third array of memory cells comprising fourth transistors (QV, DRAM including transistor and capacitor, [0004],[0006]),
wherein said second level is bonded (by micro bumps) to said first level,
wherein said second array of memory cells comprise a plurality of independently controlled memory units (different memory dies 2); and
a plurality of refresh circuits for said memory units [0005]-[0006], [0057].
Norman et al.’094 does not disclose the device further comprising a fifth level disposed on top of the fourth level, wherein the fifth level comprises single crystal silicon. However, Hwang et al. discloses a fifth level (100) comprising single crystal silicon on top of a fourth level (260). Note Figures 25-31 and [0062] of Hwang et al. Therefore, it would have been obvious to one of ordinary skills in the art at the time the invention was made to form the device of Norman et al.’094 having a fifth level, such as taught by Hwang et al. in order to form a common source plate to perform the desired function.
Norman et al.’094 and Hwang et al. do not disclose a plurality of redundancy memory cells. However, Norman et al.’889 discloses a device comprising a plurality of redundancy memory cells. Note [0058] and [0068] of Norman et al.’889. Therefore, it would have been obvious to one of ordinary skills in the art at the time the invention was made to form the device of Norman et al.’094 and Hwang et al. comprising a plurality of redundancy memory cells, such as taught by Norman et al.’889 in order to correct the error events.
Regarding claim 16, Norman et al.’094, Hwang et al. and Norman et al.’889 disclose memory control circuits comprise cache memory (Abstract, [0013], etc.)
Regarding claim 17, Norman et al.’094, Hwang et al. and Norman et al.’889 disclose a charge trap layer (ONO, [0006]).
Regarding claim 19, Norman et al.’094, Hwang et al. and Norman et al.’889 disclose a plurality of OTP fuses ([0058] and [0068]).
Claim(s) 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Norman et al. (US 2021/0248094, hereafter Norman et al.’094) in view of Hwang et al. (US 2022/0139821) and Norman et al. (US 2020/0326889, hereafter Norman et al.’889).and further in view of Tanzawa (US 2012/0273862).
Norman et al.’094, Hwang et al. and Norman et al.’889 disclose the claimed invention including the device as explained in the above rejection. Norman et al.’094, Hwang et al. and Norman et al.’889 do not disclose a transistor channel of at least one of the second transistors comprises polysilicon. However, Tanzawa disclose a transistor channel (118, 120) comprises polysilicon. Note Figure 1 and [0028] of Tanzawa. Therefore, it would have been obvious to one of ordinary skills in the art at the time the invention was made to form the transistor channel of Norman et al.’094, Hwang et al. and Norman et al.’889 comprising polysilicon, such as taught bv Tanzawa in order to have the desired conductivity.
Conclusion
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/HUNG K VU/ Primary Examiner, Art Unit 2897