DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 12,396,284 (hereinafter “Pat-284”). Although the claims at issue are not identical, they are not patentably distinct from each other because Pat-284 discloses all claimed limitations. See rejections below.
Regarding Claim 1, Pat-284 discloses a method for fabricating an integrated device, the method comprising: forming a first level comprising a first mono-crystal layer (see claim 1), wherein forming said first level comprises forming a plurality of single crystal transistors (see claim 1), a plurality of pixel control circuits, and a plurality of recessed channel transistors therein (the plurality of pixel control circuits and the plurality of recessed channel transistors in claim 1 of Pat-284 may formed in either the first level or the third level, where transistors are provided); disposing an overlying oxide on top of said first level (see claim 1); providing a second level comprising a second mono-crystal layer (see claim 1), wherein said second mono-crystal layer comprises a plurality of image sensors (see claim 1); bonding said second level to said first level via an oxide-to-oxide bond such that said second level overlays said oxide (see claim 1); and comprising disposing a third level underneath said first level (see claim 1), wherein said third level comprises a plurality of third transistors (see claim 1), and wherein said plurality of third transistors each comprise a single crystal channel (see claim 1).
Regarding Claim 2, Pat-284 discloses wherein providing said second level comprises providing a second mono-crystal layer having a thickness of less than 5 microns (see claim 2).
Regarding Claim 3, Pat-284 discloses wherein disposing said third level comprises forming a plurality of landing pads therein (see claim 3).
Regarding Claim 4, Pat-284 discloses wherein forming said first level further comprises forming alignment marks in said first mono-crystal layer (see claim 4), and wherein said bonding comprises aligning said second level to said alignment marks (see claim 4).
Regarding Claim 5, Pat-284 discloses further comprising: forming a plurality of memory circuits in at least one of said first level or said third level (the plurality of memory circuits in claim 5 of Pat-284 may formed in either the first level or the third level, where transistors are provided).
Regarding Claim 6, Pat-284 discloses wherein the fabricated integrated device comprises at least three electrically isolated single crystal layers (see claim 6).
Regrading Claim 7, Pat-284 discloses further comprising: forming a direct electrical connection between each of said plurality of image sensors and at least one of said plurality of pixel control circuits (see claim 7).
Regarding Claim 8, Pat-284 discloses a method for fabricating an integrated device, the method comprising: forming a first level comprising a first mono-crystal layer (see claim 8), wherein forming said first level comprises forming a plurality of single crystal transistors (see claim 8), a plurality of pixel control circuits, and a plurality of metal gate transistors therein (the plurality of pixel control circuits and the plurality of metal gate transistors in claim 8 of Pat-284 may formed in either the first level or the third level, where transistors are provided); disposing an overlying oxide on top of said first level (see claim 8); providing a second level comprising a second mono-crystal layer (see claim 8), wherein said second mono-crystal layer comprises a plurality of image sensors (see claim 8); bonding said second level to said first level via an oxide-to-oxide bond such that said second level overlays said oxide (see claim 8); and comprising disposing a third level underneath said first level (see claim 8), wherein said third level comprises a plurality of third transistors (see claim 8), and wherein said plurality of third transistors each comprise a single crystal channel (see claim 8).
Regarding Claim 9, Pat-284 discloses wherein providing said second level comprises providing a second mono-crystal layer having a thickness of less than 5 microns (see claim 9).
Regarding Claim 10, Pat-284 discloses wherein disposing said third level comprises forming a plurality of landing pads therein (see claim 10).
Regarding Claim 11, Pat-284 discloses wherein forming said first level further comprises forming alignment marks in said first mono-crystal layer (see claim 11), and wherein said bonding comprises aligning said second level to said alignment marks (see claim 11).
Regarding Claim 12, Pat-284 discloses further comprising: forming a plurality of memory circuits in at least one of said first level or said third level (the plurality of memory circuits in claim 12 of Pat-284 may formed in either the first level or the third level, where transistors are provided).
Regarding Claim 13, Pat-284 discloses wherein the fabricated integrated device comprises at least three electrically isolated single crystal layers (see claim 13).
Regarding Claim 14, Pat-284 discloses further comprising: forming a direct electrical connection between each of said plurality of image sensors and at least one of said plurality of pixel control circuits (see claim 14).
Regarding Claim 15, Pat-284 discloses a method for fabricating an integrated device, the method comprising: forming a first level comprising a first mono-crystal layer (see claim 15), wherein forming said first level comprises forming a plurality of single crystal transistors (see claim 15), a plurality of pixel control circuits, and a plurality of recessed channel transistors therein (the plurality of pixel control circuits and the plurality of recessed channel transistors in claim 15 of Pat-284 may formed in either the first level or the third level, where transistors are provided); disposing an overlying oxide on top of said first level (see claim 15); providing a second level comprising a second mono-crystal layer (see claim 15), wherein said second mono-crystal layer comprises a plurality of image sensors (see claim 15); aligning said second level to said first level such that said plurality of image sensors are aligned to said plurality of single crystal transistors with a less than 600 nm alignment error (see claim 15); bonding said aligned second level to said first level via an oxide-to-oxide bond such that said second level overlays said oxide (see claim 15); and comprising disposing a third level underneath said first level (see claim 15), wherein said third level comprises a plurality of third transistors (see claim 15), and wherein said plurality of third transistors each comprise a single crystal channel (see claim 15).
Regarding Claim 16, Pat-284 discloses wherein providing said second level comprises providing a second mono-crystal layer having a thickness of less than 5 microns (see claim 16).
Regarding Claim 17, Pat-284 discloses wherein disposing said third level comprises forming a plurality of landing pads therein (see claim 17).
Regarding Claim 18, Pat-284 discloses wherein forming said first level further comprises forming alignment marks in said first mono-crystal layer (see claim 18), and wherein said aligning comprises aligning said second level to said alignment marks (see claim 18).
Regarding Claim 19, Pat-284 discloses further comprising: forming a plurality of memory circuits in at least one of said first level or said third level (the plurality of memory circuits in claim 19 of Pat-284 may formed in either the first level or the third level, where transistors are provided).
Regarding Claim 20, Pat-284 discloses wherein the fabricated integrated device comprises at least three electrically isolated single crystal layers (see claim 20).
Claims 1, 2 and 4-7 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 2 and 4-7 of U.S. Patent No. 12,080,743 (hereinafter “Pat-743”). Although the claims at issue are not identical, they are not patentably distinct from each other because Pat-743 discloses all claimed limitations. See rejections below.
Regarding Claim 1, Pat-743 discloses a method for fabricating an integrated device, the method comprising: forming a first level comprising a first mono-crystal layer (see claim 1), wherein forming said first level comprises forming a plurality of single crystal transistors (see claim 1), a plurality of pixel control circuits (the plurality of pixel control circuits in claim 1 of Pat-743 may formed in either the first level or the third level, where transistors are provided), and a plurality of recessed channel transistors therein (the plurality of recessed channel transistors in claim 5 of Pat-743 may formed in either the first level or the third level, where transistors are provided); disposing an overlying oxide on top of said first level (see claim 1); providing a second level comprising a second mono-crystal layer (see claim 1), wherein said second mono-crystal layer comprises a plurality of image sensors (see claim 1); bonding said second level to said first level via an oxide-to-oxide bond such that said second level overlays said oxide (see claim 1); and comprising disposing a third level underneath said first level (see claim 1), wherein said third level comprises a plurality of third transistors (see claim 1), and wherein said plurality of third transistors each comprise a single crystal channel (see claim 1).
Regarding Claim 2, Pat-743 discloses wherein providing said second level comprises providing a second mono-crystal layer having a thickness of less than 5 microns (see claim 2).
Regarding Claim 4, Pat-743 discloses wherein forming said first level further comprises forming alignment marks in said first mono-crystal layer (see claim 4), and wherein said bonding comprises aligning said second level to said alignment marks (see claim 4).
Regarding Claim 5, Pat-743 discloses further comprising: forming a plurality of memory circuits in at least one of said first level or said third level (the plurality of memory circuits in claim 1 of Pat-743 may formed in either the first level or the third level, where transistors are provided).
Regarding Claim 6, Pat-743 discloses wherein the fabricated integrated device comprises at least three electrically isolated single crystal layers (see claim 6).
Regrading Claim 7, Pat-743 discloses further comprising: forming a direct electrical connection between each of said plurality of image sensors and at least one of said plurality of pixel control circuits (see claim 7).
Claims 1, 2, 4-7, 15, 16, 19 and 20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 2, 4-9 and 11-14 of U.S. Patent No. 11,929,372 (hereinafter “Pat-372”) in view of Koyanagi (US Pub. 2005/0029643). See rejections below.
Regarding Claim 1, Pat-372 discloses a method for fabricating an integrated device, the method comprising: forming a first level comprising a first mono-crystal layer (see claim 1), wherein forming said first level comprises forming a plurality of single crystal transistors (see claim 1), a plurality of pixel control circuits (the plurality of pixel control circuits in claim 1 of Pat-372 may formed in either the first level or the third level, where transistors are provided), and a plurality of recessed channel transistors therein (the plurality of recessed channel transistors in claim 5 of Pat-372 may formed in either the first level or the third level, where transistors are provided); disposing an overlying oxide on top of said first level (see claim 1); providing a second level comprising a second mono-crystal layer (see claim 1), wherein said second mono-crystal layer comprises a plurality of image sensors (see claim 1); bonding said second level to said first level via an oxide-to-oxide bond such that said second level overlays said oxide (see claim 1); and comprising disposing a third level underneath said first level (see claim 1), wherein said third level comprises a plurality of third transistors (see claim 1).
Pat-372 fails to disclose explicitly wherein said plurality of third transistors each comprise a single crystal channel.
However, Koyanagi discloses active regions for transistors are formed from a p-type single-crystal silicon substrate 21 (page 7, paragraph 131).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to form a single-crystal channel for a transistor, as taught by Koyanagi, in order to provide superior carrier mobility, and to reduce scattering of charge carriers as they move through the channel, leading to lower resistance and improved transistor efficiency.
Regarding Claim 2, Pat-372 discloses wherein providing said second level comprises providing a second mono-crystal layer having a thickness of less than 5 microns (see claim 2).
Regarding Claim 4, Pat-372 discloses wherein forming said first level further comprises forming alignment marks in said first mono-crystal layer (see claim 4), and wherein said bonding comprises aligning said second level to said alignment marks (see claim 4).
Regarding Claim 5, Pat-372 discloses further comprising: forming a plurality of memory circuits in at least one of said first level or said third level (the plurality of memory circuits in claim 1 of Pat-372 may formed in either the first level or the third level, where transistors are provided).
Regarding Claim 6, Pat-372 discloses wherein the fabricated integrated device comprises at least three electrically isolated single crystal layers (see claim 6).
Regrading Claim 7, Pat-372 discloses further comprising: forming a direct electrical connection between each of said plurality of image sensors and at least one of said plurality of pixel control circuits (see claim 7).
Regarding Claim 15, Pat-372 discloses a method for fabricating an integrated device, the method comprising: forming a first level comprising a first mono-crystal layer (see claim 8), wherein forming said first level comprises forming a plurality of single crystal transistors (see claim 8), a plurality of pixel control circuits (the plurality of pixel control circuits in claim 13 of Pat-372 may formed in the first level, where transistors are provided), and a plurality of recessed channel transistors therein (the plurality of recessed channel transistors in claim 11 of Pat-372 may formed in the first level, where transistors are provided); disposing an overlying oxide on top of said first level (see claim 8); providing a second level comprising a second mono-crystal layer (see claim 8), wherein said second mono-crystal layer comprises a plurality of image sensors (see claim 8); aligning said second level to said first level such that said plurality of image sensors are aligned to said plurality of single crystal transistors with a less than 600 nm alignment error (less than 400 nm, alignment error; see claim 8); bonding said aligned second level to said first level via an oxide-to-oxide bond such that said second level overlays said oxide (see claim 8); and comprising disposing a third level underneath said first level (see claim 14), wherein said third level comprises a plurality of third transistors (see claim 14).
Pat-372 fails to disclose explicitly wherein said plurality of third transistors each comprise a single crystal channel.
However, Koyanagi discloses active regions for transistors are formed from a p-type single-crystal silicon substrate 21 (page 7, paragraph 131).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to form a single-crystal channel for a transistor, as taught by Koyanagi, in order to provide superior carrier mobility, and to reduce scattering of charge carriers as they move through the channel, leading to lower resistance and improved transistor efficiency.
Regarding Claim 16, Pat-372 discloses wherein providing said second level comprises providing a second mono-crystal layer having a thickness of less than 5 microns (see claim 9).
Regarding Claim 19, Pat-372 discloses further comprising: forming a plurality of memory circuits in at least one of said first level or said third level (the plurality of memory circuits in claim 8 of Pat-372 may formed in the first level, where transistors are provided).
Regarding Claim 20, Pat-372 discloses wherein the fabricated integrated device comprises at least three electrically isolated single crystal layers (see claim 12).
Allowable Subject Matter
Claims 1-20 will be allowed after overcoming the nonstatutory double patenting rejections, as shown above.
Koyanagi discloses an image sensor having a three-layer structure comprising an output layer (transistors) (fig. 1), a light-receiving element layer (photodiodes) (fig. 1), and a light-introducing layer (microlenses) (fig. 1). However, Koyanagi differs from the present invention because Koyanagi fails to disclose a first level comprising a plurality of pixel control circuits and a plurality of recessed channel transistors, a third level disposed underneath a first level comprising a plurality of third transistors; and a plurality of image sensors is aligned to a plurality of single crystal transistors with a less than 600 nm alignment error.
The following is an examiner’s statement of reasons for allowance:
Claim 1 recites forming the first level comprises forming a plurality of single crystal transistors, a plurality of pixel control circuits, and a plurality of recessed channel transistors therein; bonding the second level to the first level via an oxide-to-oxide bond such that the second level overlays the oxide; and comprising disposing a third level underneath the first level, wherein the third level comprises a plurality of third transistors.
Claim 8 recites forming the first level comprises forming a plurality of single crystal transistors, a plurality of pixel control circuits, and a plurality of metal gate transistors therein; bonding the second level to the first level via an oxide-to-oxide bond such that the second level overlays the oxide; and comprising disposing a third level underneath the first level, wherein the third level comprises a plurality of third transistors.
Claim 15 recites forming the first level comprises forming a plurality of single crystal transistors, a plurality of pixel control circuits, and a plurality of recessed channel transistors therein; aligning the second level to the first level such that the plurality of image sensors are aligned to the plurality of single crystal transistors with a less than 600 nm alignment error; bonding the aligned second level to the first level via an oxide-to-oxide bond such that the second level overlays the oxide; and comprising disposing a third level underneath the first level, wherein the third level comprises a plurality of third transistors.
These features in combination with the other elements of the claim are neither disclosed nor suggested by the prior art of record.
Claims 2-7, 9-14 and 16-20 variously depend from claim 1, 8 or 15, so they will be allowed for the same reason.
Conclusion
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/CHEUNG LEE/Primary Examiner, Art Unit 2812 February 13, 2026