Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Acknowledgement
This office action is in response to the communication filed on 03/20/2026.
Claims 1-20 are currently pending in the present application. Claim 1 has been amended.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1 has been considered but are moot because the new ground of double patenting rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Claim(s) 1, 3-5 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-5 of U.S. Patent No. 12,100,646 B2 (hereinafter Patent’646) in view of claim 7 of U.S. Patent No. 12,136,562 B2 (hereinafter Patent’562) and claim 3 of U.S. Patent No. 8,482,051 B2 (hereinafter Patent’051), as shown below.
Application 19/280,176
U.S. Patent No. 12,100,646 B2
1. A semiconductor device, the device comprising:
a first silicon layer comprising a first single crystal silicon;
a first metal layer disposed over said first silicon layer;
a second metal layer disposed over said first metal layer;
a second level comprising a second single crystal silicon and a plurality of transistors,
said second level is disposed over said second metal layer;
a third metal layer disposed over said second level;
a fourth metal layer disposed over said third metal layer;
a via disposed through said second level,
wherein said via has a diameter of less than 450 nm,
wherein said second level thickness is less than four microns; and
at least one temperature sensor.
1. A semiconductor device, the device comprising:
a first silicon layer comprising a first single crystal silicon layer;
…
a first metal layer disposed over said plurality of first transistors;
a second metal layer disposed over said first metal layer;
…
a second level comprising a plurality of second transistors,
said second level is disposed over said third metal layer;
a third level comprising a plurality of third transistors, said third level is disposed over said second level;
a fourth metal layer disposed over said third level;
a fifth metal layer disposed over said fourth metal layer;
a via disposed through said second level,
…
wherein said device comprises at least one temperature sensor,
…
2. The device according to claim 1, wherein an average thickness of said second level is less than two microns.
4. The device according to claim 1, wherein said via has a diameter of less than 450 nm.
3. The device according to claim 1, wherein said fourth metal layer is aligned to said first metal layer with a less than 40 nm alignment error.
3. The device according to claim 1, wherein said fourth metal layer is aligned to said first metal layer with a less than 100 nm alignment error.
4. The device according to claim 1, wherein at least one of said plurality of transistors comprises a metal gate.
1…wherein at least one of said plurality of second transistors comprises a metal gate…
5. The device according to claim 1, wherein a typical thickness of said second metal layer is greater than a typical thickness of said third metal layer by at least 50%.
5. The device according to claim 1, wherein an average thickness of said second metal layer is greater than an average thickness of said third metal layer by at least 50%.
Although the claims at issue are not identical, they are not patentably distinct from each other. The italicized claim limitations in claim 1 of the Application 19/280,176 are anticipated from the italicized claim limitations of claim 1 of Patent’646.
However, the claim limitation in claim 1 of the Application 19/280,176 “a second level comprising a second single crystal silicon” is neither anticipated nor obvious from claims of the Patent’646.
In the same field of endeavor, Patent’562 discloses in claim 7, a 3D semiconductor device wherein said second level comprises a second single crystal layer.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to employ the teachings of Patent’562 into the 3D semiconductor device of Patent’646 in order to form transistors in a low defect density silicon layer (Col. 9, last paragraph and col. 10, 1st paragraph).
Furthermore, the claim limitation in claim 1 of the Application 19/280,176 “wherein at least one of said plurality of transistors comprises a gate all- around structure” is neither anticipated nor obvious from claims of the Patent’646 in view of Patent’562.
In the same field of endeavor, Patent’051 (US 8482051 B2) discloses in claim 3, a 3D semiconductor device wherein at least one transistor comprises a gate all- around structure.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to employ the teachings of Patent’051 into the 3D semiconductor device of Patent’646 in view of Patent’562 in order to reduce its area and suppress the occurrence of leakage current therein (Col. 4, lines 50-65).
Claim(s) 2 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of U.S. Patent No. 12,100,646 B2 (hereinafter Patent’646) in view of claim 2 of U.S. Patent No. 11,482,494 B1 (hereinafter Patent’494), as shown below.
Regarding claim 2 of the Application 19/280,176, the claim limitation “wherein said via comprises tungsten” is neither anticipated nor obvious from claims of the Patent’646.
In the same field of endeavor, Patent’494 discloses in claim 2, a 3D semiconductor device wherein said via comprises tungsten.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to employ the teachings of Patent’494 into the 3D semiconductor device of Patent’646 in order to form vias with high thermal conductivity and high melting point materials (Col. 57, 1st paragraph).
Allowable Subject Matter
Claims 1-5 would be allowable if the double patenting rejections are overcome.
Claims 6-7 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 8-20 are allowed over prior art of record.
The following is an Examiner’s statement of reasons for allowance, which paraphrases and summarizes the claimed invention without intending to be limiting, wherein the legally defined scope of the claimed invention is defined by the allowed claims themselves in view of the written description under 35 U.S.C. §112. The statement is not intended to necessarily state all the reasons for allowance or all the details why claims are allowed and should not be written to specifically or impliedly state that all the reasons for allowance are set forth (MPEP §1302.14).
The cited prior art of record, Or-Bach et al. US PGPUB no. 20120248595 A1 (hereinafter, Or-Bach’595) and Farooq et al. (US 20100193964 A1; hereinafter “Farooq”) have been found to be the closest prior art.
Regarding independent Claim 1:
Farooq discloses a semiconductor device (fig. 12), the device comprising:
a first level (50, 42) (hereinafter “LVL1”) (¶ 0039),
wherein said first level comprises a first layer (the layer containing the devices 50; hereinafter “L1”), said first layer (L1) comprising first transistors 50, and
wherein said first level (LVL1) comprises first, second and third metal layers (46, a metal layer above 46 and 54);
a second level (22, 24) (hereinafter “LVL2”) (¶ 0037) overlaying said first level (LVL1),
wherein said second level comprises a third layer (the layer containing the devices 22; hereinafter “L3”), said third layer (L3) comprising second transistors 22, and
wherein said second level comprises a fourth and fifth metal layers (28, 34);
a via disposed through the second level (LVL2).
None of the prior art of record cited above or in the attached PTO-892 teaches or suggests, alone or in combination, all the limitations of independent claim 1 including first and second levels comprising single crystal silicon layers, wherein said via has a diameter of less than 450 nm, wherein said second level thickness is less than four microns; and at least one temperature sensor.
Regarding independent Claim 8:
Farooq discloses a semiconductor device (fig. 12), the device comprising:
a first level (50, 42) (hereinafter “LVL1”) (¶ 0039),
wherein said first level comprises a first layer (the layer containing the devices 50; hereinafter “L1”), said first layer (L1) comprising first transistors 50, and
wherein said first level (LVL1) comprises first, second and third metal layers (46, a metal layer above 46 and 54);
a second level (22, 24) (hereinafter “LVL2”) (¶ 0037) overlaying said first level (LVL1),
wherein said second level comprises a third layer (the layer containing the devices 22; hereinafter “L3”), said third layer (L3) comprising second transistors 22, and
wherein said second level comprises a fourth and fifth metal layers (28, 34);
a via disposed through the second level (LVL2).
None of the prior art of record cited above or in the attached PTO-892 teaches or suggests, alone or in combination, all the limitations of independent claim 8 including first and second levels comprising single crystal silicon layers, wherein said via has a diameter of less than 450 nm, wherein said second level thickness is less than four microns; and a plurality of decoupling capacitors.
Dependent claims 9-14 are allowed for the same reasons.
Regarding independent Claim 15:
Farooq discloses a semiconductor device (fig. 12), the device comprising:
a first level (50, 42) (hereinafter “LVL1”) (¶ 0039),
wherein said first level comprises a first layer (the layer containing the devices 50; hereinafter “L1”), said first layer (L1) comprising first transistors 50, and
wherein said first level (LVL1) comprises first, second and third metal layers (46, a metal layer above 46 and 54);
a second level (22, 24) (hereinafter “LVL2”) (¶ 0037) overlaying said first level (LVL1),
wherein said second level comprises a third layer (the layer containing the devices 22; hereinafter “L3”), said third layer (L3) comprising second transistors 22, and
wherein said second level comprises a fourth and fifth metal layers (28, 34);
a via disposed through the second level (LVL2).
None of the prior art of record cited above or in the attached PTO-892 teaches or suggests, alone or in combination, all the limitations of independent claim 15 including first and second levels comprising single crystal silicon layers, wherein said via has a diameter of less than 450 nm, wherein said second level thickness is less than four microns; wherein said second level comprises a power delivery grid; and a heat removal path, wherein said heat removal path comprises a pathway from said power delivery grid to an external surface of said device.
Dependent claims 16-20 are allowed for the same reasons.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NILUFA RAHIM whose telephone number is (571)272-8926. The examiner can normally be reached M-F 9am-5:30pm EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Yara J. Green can be reached at (571) 270-3035. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/NILUFA RAHIM/Primary Examiner, Art Unit 2893