Detailed Action
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restriction
Applicant’s election without traverse of Group II in the reply filed on 19 March 2026 is acknowledged.
Claims 1-9 cancelled pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 19 March 2026.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the feature of claim 18 wherein “a backside interface between the backside silicide and the source is curved down towards the backside power rail” must be shown or the feature(s) canceled from the claim(s). In figures 9-15 this region is shown to curve away from the backside power rail, not towards it. No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections 35 U.S.C § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 10-11 and 15-17 are rejected under 35 U.S.C. 103 as being unpatentable over Chung et al. (US Pub 20220359700), hereinafter referred to as Chung and Yu et al.(US Pub. 20220359685), hereinafter referred to as Yu.
Regarding claim 10, Chung teaches a device structure comprising:
a gate (Chung, 230, Figs 8B 25B, see 25B below, para. 40-41) disposed between a first source/drain (Chung, 190a, Fig. 25B, para. 35) and a second source/drain (Chung, 190B, Fig. 25B, para. 35 ); a first interconnect structure (Chung, 25B) disposed over a first side of the first source/drain, wherein the first interconnect structure includes a source/drain contact (Chung, 260, Fig. 25B, para 45) disposed on the first side of the first source/drain, a first source/drain via disposed on the source/drain contact (Chung, 270, Fig. 25B para. 46, 270 is a multi-layer interconnection which includes vias), and a first power rail disposed on the first source/drain via (Chung, 270, Fig. 25B para. 46, 270 is a multi-layer interconnection which includes metal lines); and a second interconnect structure (Chung, Fig. 25B) disposed over a second side of the first source/drain, wherein the second side of the first source/drain is opposite the first side of the first source/drain and the second interconnect structure includes a second source/drain via (Chung, 340, Fig. 25B, para. 59) disposed on the second side of the first source/drain.
Chung does not explicitly teach a second power rail disposed on the second source/drain via. However, Chung does teach that the first source drain, can be further connected to external circuits from a backside of the semiconductor device through the backside via (Chung, para. 61).
Yu teaches a backside power rail (Yu, 103, Fig. 13, para. 16) connected to a source/drain region (Yu, 110B, Fig. 13, para. 17) by an interconnect structure (Yu, 104, Fig. 13, para 16).
Therefore it would have been obvious to one having ordinary skill in the art before the filing date of the invention to combine the device of Chung with the backside power rail of Yu to connect it to external circuits (Chung, para. 61)
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Regarding claim 11, modified Chung teaches the device structure of claim 10, wherein the gate is disposed between the first source/drain and the second source/drain along a direction (Chung, Fig. 25B), the first power rail extends lengthwise along the direction (Chung, Fig 25B), and the second power rail extends lengthwise along the direction (Yu, 103, Fig 13, 103 extends on the same axis relative to the first S/D (110A, para. 17) structure and the second S/D structure (110B, para. 17)).
Regarding claim 15, modified Chung teaches the device structure of claim 10, further comprising a first silicide layer (Chung, 250, Fig. 25B, para 44) and a second silicide layer (Chung, 330, Fig. 25B, para. 58), wherein the first silicide layer is disposed between the first side of the first source/drain and the source/drain contact and the second silicide layer is disposed between the second side of the first source/drain and the second source/drain via (Chung, Fig. 25B).
Regarding claim 16, modified Chung teaches the device structure of claim 10, wherein the source/drain contact is a first source/drain contact (Chung, 190a, Fig. 25B, para. 35),
the device structure further comprising a third interconnect structure disposed over the second source/drain (Chung, 190B, Fig. 25B, para. 35), wherein the third interconnect structure includes a second source/drain contact (Chung, 260, Fig. 25B, para. 45) disposed on a first side of the second source/drain.
Regarding claim 17, modified Chung teaches the device structure of claim 10, wherein: the gate, the first source/drain, and the second source/drain belong to a transistor (Chung, para. 68); the first source/drain is a source of the transistor (Chung, 190a, Fig. 25B, para. 35); and the second source/drain is a drain of the transistor (Chung, 190b, Fig. 25B, para. 35).
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Chung and Yu as applied to claim 10 above, and further in view of Chang et al. Chang et al. (US Pub 20220367727), hereinafter referred to as Chang.
Regarding claim 12, modified Chung teaches the device structure of claim 10, wherein: the first source/drain via is disposed in an interlayer dielectric layer (Chung, para. 46).
Modified Chung does not teach the second source/drain via is disposed in a semiconductor substrate.
However, Chang teaches a semiconductor device with a backside via (Chang, 130, Fig. 30C, para. 40) which is disposed in a semiconductor substrate (Chang, 50, Fig. 30C, para. 11).
Therefore it would have been obvious to one having ordinary skill in the art before the filing date of the invention to combine the device of modified Chung with the backside via and substrate of Chang to simplify the construction of the device by providing a substrate with high etch selectivity relative to layers being formed over it in order to simplify removing those layers later (Chang, para 85).
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Claims 13-14 are rejected under 35 U.S.C. 103 as being unpatentable over Chung, Yu and Chang as applied to claim 12 above, and further in view of Chiu et al. (US Pub. 20210335783) hereinafter referred to as Chiu.
Regarding claim 13, modified Chung teaches the device structure of claim 12, but does not teach wherein a dielectric layer is disposed between sidewalls of the second source/drain via and the semiconductor substrate.
However, Chiu teaches a backside via (Chiu, 144, fig 38C, para. 107) which has a barrier layer (Chiu 142, Fig. 38C, para. 107).
Therefore it would have been obvious to one having ordinary skill in the art before the filing date of the invention to have incorporated the barrier layer of Chiu into the device of modified Chung in order to prevent metal diffusion between the via and substrate.
Regarding claim 14, modified Chung teaches the device structure of claim 13, wherein a remnant (Chung, 280, Fig 25B, para. 50) of a source/drain isolation structure is disposed between the dielectric layer and the first source/drain. The remnant of 280 is disposed on the sidewall of the via just below the source/drain feature and on the sidewall of the via, and thus would be disposed between the source/drain feature and semiconductor layer.
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Claims 18-21 and 24 are rejected under 35 U.S.C. 103 as being unpatentable over Chung, Yu and Chiu.
Regarding claim 18, Chung teaches a device structure comprising: a gate disposed between a source (Chung, 190a, Fig. 25B, para. 35) and a drain (Chung, 190b, Fig. 25B, para 35,
a frontside silicide (Chung, 250, Fig. 25b, para. 44) and a backside silicide disposed on the source (Chung, 330, Fig 25b, para. 58),
and a backside source via (Chung, 340, Fig. 25b, para. 59);
wherein the backside silicide is disposed between the source and the backside source via (Chung, Fig. 25B).
Chung does not explicitly teach wherein the source is sandwiched between and connected to a frontside power rail (Chung, 270, Fig. 25B, para. 46) and a backside power rail, nor does Chung explicitly teach a backside source via that extends from the source to the backside power rail. Chung does teach that the backside source via, which extends from the source can be further connected to external circuits (Chung, para. 61).
Yu teaches a backside power rail (Yu, 103, Fig. 13, para. 16) connected to a source/drain region (Yu, 110B, Fig. 13, para. 17) by an interconnect structure (Yu, 104, Fig. 13, para 16).
Therefore it would have been obvious to one having ordinary skill in the art before the filing date of the invention to combine the device of Chung with the backside power rail of Yu to connect it to external circuits (Chung, para. 61), thus sandwiching the source between frontside and backside power rails.
Chung also does not teach wherein a frontside interface between the frontside silicide and the source is curved up towards the frontside power rail, and a backside interface between the backside silicide and the source is curved down towards the backside power rail;
However, Chiu teaches a source frontside interface between a frontside silicide (Chiu, 110, Fig. 38C, para. 70) and a source/drain region (Chiu, 92, Fig. 38C, para.13) which is curved toward the frontside interconnect structure Chiu, 120, Fig. 38C, para. 74, examiner notes the curve is down in this figure, but the device is shown inverted). Chiu also teaches that the back side of the source can be curved toward the backside power rail (Chiu, 154, Fig. 38C, para. 108). Additionally, Chiu notes that a silicide region can be formed over the back side portion of the source drain (Chi, para. 107).
Therefore it would have been obvious to one having ordinary skill in the art to combine to teachings of Chung and Yu with the silicide configuration of Chiu to create silicide/source region interfaces that curved toward the front and back side rails respectively in order to decrease feature sizes and increase device density (Chiu, para. 9).
Regarding claim 19, modified Chung teaches the device structure of claim 18, wherein the frontside power rail belongs to a first level metallization layer of a frontside interconnect structure (Chung, 270, Fig. 25B, para. 46), and the backside power rail belongs to a first level metallization layer of a backside interconnect structure (Yu, 103, Fig. 13, para. 16).
Regarding claim 20, modified Chung teaches the device structure of claim 18, further comprising: a stack of semiconductor layers (Chung 124, Fig. 25B, para. 17) disposed between the source and the drain, wherein the gate is disposed over and wraps the stack of semiconductor layers (Chung, 230, Fig 25B/C, para. 31); an inner spacer (Chung, 180, Fig. 25B para. 31) disposed between the source and a portion of the gate disposed below a bottom of the stack of semiconductor layers; and a remnant (Chung, 280, Fig. 25B, para. 50-51) of a source/drain isolation structure disposed between the inner spacer and a sidewall of the backside source via.
Regarding claim 21, modified Chung teaches the device structure of claim 20, wherein the remnant is formed of nitride (Chung, para. 50).
Regarding claim 24, modified Chung teaches the device structure of claim 18, wherein the backside source via (Chung, 340, Fig. 25b, para. 59), extends form the backside power rail to a distance above a bottom of the gate (Chung, Fig. 25B shows 340 extending above the bottom of the lowest instance of gate 230).
Claims 22-23 are rejected under 35 U.S.C. 103 as being unpatentable over Chung, Yu and Chiu as applied to claim 18 above, and further in view of Huang et al. (US Pub. 20210202385) hereinafter referred to as Huang.
Regarding claim 22, modified Chung teaches the device structure of claim 18, but does not teach wherein the backside source via extends through a nitride layer to the backside power rail, wherein the nitride layer is sandwiched between the backside power rail and a semiconductor substrate.
However, Huang teaches a backside contact (Huang, 120, Fig. 19, para. 15) which extends through an isolation layer (Huang, 122, Fig. 19, para. 59, 122 may be made of silicon nitride) to contact a power rail (Huang, 118, Fig. 19, para. 15). Further, the isolation layer is between the power rail and the substrate (Huang, 102, Fig 19, para. 15).
Therefore it would have been obvious to one having ordinary skill in the art to combine the device of modified Chung with the isolation layer of Huang to prevent current leakage between vias.
Regarding claim 23, modified Chung teaches the device structure of claim 22, wherein the nitride layer is a first nitride layer, the backside source via (Huang, 120, Fig. 19, para. 15) extends through the semiconductor substrate (Huang, 102, Fig 19, para. 15), and a second nitride layer is disposed between the backside source via and the semiconductor substrate (Chiu, 142, Fig 38C. para. 107).
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Claims 25-29 are rejected under 35 U.S.C. 103 as being unpatentable over Chung, and Huang.
Regarding claim 25, Chung teaches a device comprising: a frontside power rail (Chung, 270, Fig. 25B, para. 46); an epitaxial source/drain structure (Chung, 190a, Fig. 25B, para. 35) disposed between the frontside power rail and the backside via (Chung, 340, Fig. 25B, para. 59), wherein the epitaxial source/drain structure (Chung, 190a, Fig. 25B, para 35) is connected to the frontside power rail by a frontside source/drain contact (Chung, 260, Fig. 25B, para. 45),
Chung does not teach that the frontside power rail is disposed over a frontside of a substrate; a backside power rail disposed over a backside of the substrate; the epitaxial source/drain structure disposed between the frontside power rail and the backside power rail, the epitaxial source/drain structure is connected to the backside power rail by a backside source/drain via, and the backside source/drain via is disposed in a substrate; and a dielectric layer is disposed between the substrate and the backside power rail, wherein the backside source/drain via extends through the dielectric layer. Chung does teach that the backside source via, which extends from the source can be further connected to external circuits (Chung, para. 61).
However, Huang teaches a substrate (Huang, 102, Fig. 19, para. 59) on which epitaxial source/drains are formed, over which a front power rail (Huang, 126, Fig. 19, para. 140 is formed, and on the backside of which a backside power rail is formed (Huang, 118, Fig. 19 para. 15), Huang also teaches a backside contact (Huang, 120 para. Fig. 19, 15) which passes from an epitaxial source/drain, through the substrate and an isolation layer (Huang, 122, Fig. 19, para.59) to contact the backside power railing.
Therefore it would have been obvious to one skilled in the art to combine the device of Chung with the substrate, rails, and isolation layer of Huang to reduce current leakage and connect it to external circuits (Chung, para. 61).
Regarding claim 26, modified Chung teaches the device of claim 25, further comprising: a backside silicide layer (Chung, 330, Fig. 25B, para. 58) disposed between the backside source/drain via and a backside of the epitaxial source/drain structure; and a frontside silicide layer (Chung, Fig. 25B, para. 44) disposed between the frontside source/drain contact and a frontside of the epitaxial source/drain structure, wherein the epitaxial source/drain structure (Chung, 190a, Fig 25B, para. 35) is disposed between the backside silicide layer and the frontside silicide layer.
Regarding claim 27, modified Chung teaches the device of claim 25, wherein the backside source/drain via (Chung, 340, Fig. 25B, para. 59), extends through a source/drain isolation structure (Chung, 280, Fig. 25B, para. 50) of the epitaxial source/drain structure (Chung, 190a Fig. 25B, para. 35) and the source/drain isolation structure is disposed between via spacers (Chung, 180, Fig. 25B, para. 31) and the epitaxial source/drain structure, wherein the via spacers are disposed along sidewalls of the backside source/drain via.
Regarding, claim 28, modified Chung teaches, the device of claim 27, wherein the dielectric layer (Huang, 122, Fig. 19, para. 17), the via spacers (Chung, 180, Fig. 25B, para 31), and the source/drain isolation (Chung, 280, Fig. 25B, para 50) structure include silicon and nitrogen (Reference paragraphs for each part show the materials).
Regarding claim 29, modified Chung teaches the device of claim 25, wherein the dielectric layer (Huang, 122, Fig. 19, para.59) abuts the substrate (Huang, 102, Fig. 19, para. 59), and the dielectric layer abuts the backside power rail (Huang, 118, Fig. 19 para. 15),
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Su et al. (US Pub. 20210391325) shows a backside power rail connected to s source through a backside via with s liner layer.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KIERAN M CUNNINGHAM whose telephone number is (571)272-9654. The examiner can normally be reached Mon-Fri 8:00-4:3.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached at 5712703042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/KIERAN M. CUNNINGHAM/Examiner, Art Unit 2893
/Britt Hanley/Supervisory Patent Examiner, Art Unit 2893
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