Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group 1 in the reply filed on 6/30/2026 is acknowledged. Claims 1-18 and 21-22 are pending. Claims 19-20 are cancelled.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3 are rejected under 35 U.S.C. 103 as being unpatentable over US20170371994A1 (Bowers) in view of US20160027499A1 (Liaw).
Regarding Claim 1, Bowers discloses an integrated circuit (Figs. 2B, Para. [0029]) comprising: a first transistor of a first type (see annotated Fig. 2B below – 214b is a gate, and overlaps diffusion regions 204a and 204b, see Para. [0027], forming a 5-Fin nfet); a floating gate transistor of the first type (see annotated Fig. 2B below, - 216a can be configured to be a floating gate (Para. [0029]) and is also an F-fin nfet), and being coupled to the first transistor (Fig. 2B, they share the same diffusion region 204b), and being separated from the first transistor in a first direction (see annotated Fig. 2B below), the floating gate transistor comprising: a first drain coupled to a first voltage supply (204b coupled to GND – Para. [0034]); a first source coupled to the first voltage supply and the first drain (204c coupled to GND – Para. [0034]), and a floating gate extending in a second direction different from the first direction (216a extends perpendicular to the first direction – see annotated Fig. 2B below), being located on a first level (the gate is inherently located on a different level than the fins and the diffusion region), and the floating gate being electrically floating (Para. [0034]); a second transistor of a second type different from the first type (see annotated Fig. 2B below, where the 3-fin pfet is a transistor of a different type than the nfet – Para. [0026]), the second transistor being separated from the first transistor in the second direction (see annotated Fig. 2b below), the second transistor comprising: a first gate extending in the second direction (see annotated Fig. 2B below), and being separated from the floating gate in the first direction (Fig. 2b, el. 214b, Para. [0026]), and power/ground rail connections (Para. [0034]).
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Bowers does not disclose a first conductive portion extending in the first direction, being on a second level different from the first level, and overlapping at least the floating gate, the first conductive portion is not electrically coupled to the floating gate; and a second conductive portion extending in the first direction, being on the second level, overlapping at least the first gate, and being separated from the first conductive portion in the second direction, and the second conductive portion being electrically coupled to the second transistor; and a third conductive portion extending in the first direction, being on the second level, and overlapping at least the first drain or the first source.
Liaw discloses an integrated circuit (Fig. 4C, Para. [0040]) with nfinFets and pfinFets (Para. [0032]), and multiple conductive portions on a different level overlapping the gates of the fets (Fig. 4c, Para. [0037]).
It would have been obvious to one skilled in the art before the effective filing date of the
claimed invention to add conductive portions on a different level and connect them to the gate, source and drain portions as disclosed by Liaw. The idea of connection power and signal lines is already disclosed in Bowers (Para. [0034]) and the use of perpendicular connecting structures on a different level from the gate/source/drain regions is disclosed in Liaw. Combining them in the manner described in the first claim would be obvious to a person of ordinary skill in the art, as this is a common way to connect power/signal lines to the gates/source/drains of the various transistors.
Regarding Claim 2, Bowers in view of Liaw discloses the integrated circuit of claim 1, further comprising: a first active region extending in the first direction (Bowers, Fig. 2B, regions 204a, 204b, and 204c), and being on a third level different from the first level and the second level (this is inherent in the structure of the device), the first active region being overlapped by the floating gate and the first gate (Fig. 2B), and the first active region comprising: a first region corresponding to a first source/drain region of the floating gate transistor, and being coupled to the first voltage supply (Bowers, Fig. 2B, el. 204c, Para. [0034] – which discloses that 204c is coupled to ground); a second region corresponding to a second source/drain region of the floating gate and the first transistor, and being coupled to the first voltage supply (Bowers, Fig. 2b, 204b, Para. [0034]); and a third region corresponding to a third source/drain region of the first transistor (Bowers, Fig. 2b, el. 204a).
Regarding Claim 3, Bowers in view of Liaw discloses the integrated circuit of Claim 2, further comprising: a second active region extending in the first direction (Bowers, Fig. 2B, els. 202a, 202b, 202c), being on the third level (this is inherent in the structure of the device), and being separated from the first active region in the second direction (Fig. 2B, where the second active region is above the first active region), the second active region being overlapped by at least the first gate (Fig. 2b, where the first gate 214b overlaps the second active region), and the second active region comprising: a fourth region corresponding to a fourth source/drain region of the second transistor, and being coupled to a second voltage supply different from the first voltage supply (Bowers, Fig. 2B, el. 202b, Para. [0026], which discloses that this region is coupled to VDD); and a fifth region corresponding to a fifth source/drain region of the second transistor (Bowers, Fig. 2B, el. 202a).
Claims 4-5 are rejected as being unpatentable over Bowers in view of Liaw.
Regarding Claims 4-5, Bowers in view of Liaw discloses the integrated circuit of claim 3.
Bowers in view of Liaw does not disclose a fourth conductive portion extending in the first direction, being on the second level, and overlapping the floating gate, and being adjacent to the second conductive portion, the fourth conductive portion is not electrically coupled to the floating gate; and does not disclose a first via between the third conductive portion and the first gate, the first via electrically coupling the third conductive portion and the first gate together; anda second via between the second conductive portion and the fifth region, the second via electrically coupling the second conductive portion and the fifth region together.
However, as discussed above, Liaw discloses using multiple conductors to connect power/gnd and signal lines to the various transistors, and Bowers discloses the use of vias to interconnect power/gnd to the various terminals of the transistor (Para. [0034]).
Therefore, it would have been obvious to one skilled in the art before the effective filing date of the claimed invention to add extra conductors and vias in the places disclosed for the benefit of connecting the various power/gnd and signal lines to the various transistors.
Claims 12-13 are rejected as being unpatentable over Bowers in view of Liaw.
Regarding Claim 12, Bowers discloses an integrated circuit (Figs. 2B, Para. [0029]) comprising: a first transistor of a first type (see annotated Fig. 2B above – 214b is a gate, and overlaps diffusion regions 204a and 204b, see Para. [0027], forming a 5-Fin nfet); a floating gate transistor (see annotated Fig. 2B below, - 216a can be configured to be a floating gate (Para. [0029])) coupled to the first transistor (Fig. 2B, they share the same diffusion region 204b), and being separated from the first transistor in a first direction (see annotated Fig. 2B below), the floating gate transistor comprising: a drain coupled to a first voltage supply (204b coupled to GND – Para. [0034]); a source coupled to the first voltage supply (204c coupled to GND – Para. [0034]), and a floating gate extending in a second direction different from the first direction (216a extends perpendicular to the first direction – see annotated Fig. 2B below), being located on a first level (the gate is inherently located on a different level than the fins and the diffusion region), and the floating gate being electrically floating (Para. [0034]); a second transistor of a second type different from the first type (see annotated Fig. 2B below, where the 3-fin pfet is a transistor of a different type than the nfet – Para. [0026]), the second transistor being separated from the first transistor in the second direction (see annotated Fig. 2b below), the second transistor comprising: a first gate extending in the second direction (see annotated Fig. 2B below), and being separated from the floating gate in the first direction (Fig. 2b, el. 214b, Para. [0026]), and power/ground rail connections (Para. [0034]).
Bowers does not disclose a first conductor extending in the first direction, being on a second level different from the first level, and overlapping at least the floating gate, the first conductor is not electrically coupled to the floating gate; and a second conductor extending in the first direction, being on the second level, overlapping at least the first gate, and being separated from the first conductor in the second direction, and the second conductor being electrically coupled to the second transistor.
Liaw discloses an integrated circuit (Fig. 4C, Para. [0040]) with nfinFets and pfinFets (Para. [0032]), and multiple conductive portions on a different level overlapping the gates of the fets (Fig. 4c, Para. [0037]).
It would have been obvious to one skilled in the art before the effective filing date of the
claimed invention to add conductive portions on a different level and connect them to the gate, source and drain portions as disclosed by Liaw. The idea of connection power and signal lines is already disclosed in Bowers (Para. [0034]) and the use of perpendicular connecting structures on a different level from the gate/source/drain regions is disclosed in Liaw. Combining them in the manner described in the first claim would be obvious to a person of ordinary skill in the art, as this is a common way to connect power/signal lines to the gates/source/drains of the various transistors.
Regarding Claim 13, Bowers in view of Liaw discloses the integrated circuit of Claim 12, further comprising: a first active region extending in the first direction (Bowers, Fig. 2B, regions 204a, 204b, and 204c), and being on a third level different from the first level and the second level (this is inherent in the structure of the device), the first active region being overlapped by the floating gate and the first gate (Fig. 2B), and the first active region comprising: a first region corresponding to a first source/drain region of the floating gate transistor, and being coupled to the first voltage supply (Bowers, Fig. 2B, el. 204c, Para. [0034] – which discloses that 204c is coupled to ground); a second region corresponding to a second source/drain region of the floating gate and the first transistor, and being coupled to the first voltage supply (Bowers, Fig. 2b, 204b, Para. [0034]); and a third region corresponding to a third source/drain region of the first transistor (Bowers, Fig. 2b, el. 204a), and a second active region extending in the first direction (Bowers, Fig. 2B, els. 202a, 202b, 202c), being on the third level (this is inherent in the structure of the device), and being separated from the first active region in the second direction (Fig. 2B, where the second active region is above the first active region), the second active region being overlapped by at least the first gate (Fig. 2b, where the first gate 214b overlaps the second active region), and the second active region comprising: a fourth region corresponding to a fourth source/drain region of the second transistor, and being coupled to a second voltage supply different from the first voltage supply (Bowers, Fig. 2B, el. 202b, Para. [0026], which discloses that this region is coupled to VDD); and a fifth region corresponding to a fifth source/drain region of the second transistor (Bowers, Fig. 2B, el. 202a).
Claims 21-22 are rejected under 35 U.S.C. 103 as being unpatentable over Bowers in view of Liaw.
Regarding Claim 21, Bowers discloses an integrated circuit (Figs. 2B, Para. [0029]) comprising: a first transistor of a first type (see annotated Fig. 2B above – 214b is a gate, and overlaps diffusion regions 204a and 204b, see Para. [0027], forming a 5-Fin nfet); a floating gate transistor of the first type (see annotated Fig. 2B below, - 216a can be configured to be a floating gate (Para. [0029]) and is also an F-fin nfet), and being coupled to the first transistor (Fig. 2B, they share the same diffusion region 204b), and being separated from the first transistor in a first direction (see annotated Fig. 2B below), the floating gate transistor comprising: a drain coupled to a first voltage supply (204b coupled to GND – Para. [0034]); a source coupled to the first voltage supply and the first drain (204c coupled to GND – Para. [0034]), and a floating gate extending in a second direction different from the first direction (216a extends perpendicular to the first direction – see annotated Fig. 2B below), being located on a first level (the gate is inherently located on a different level than the fins and the diffusion region), and the floating gate being electrically floating (Para. [0034]); a second transistor of a second type different from the first type (see annotated Fig. 2B above, where the 3-fin pfet is a transistor of a different type than the nfet – Para. [0026]), the second transistor being separated from the first transistor in the second direction (see annotated Fig. 2b above), the second transistor comprising: a first gate extending in the second direction (see annotated Fig. 2B above), and being separated from the floating gate in the first direction (Fig. 2b, el. 214b, Para. [0026]), and power/ground rail connections (Para. [0034]) connected to the gate/source/drain regions by vias (Para. [0034]).
Bowers does not disclose a first conductor extending in the first direction, being on a first level, and overlapping at least the floating gate, the first conductor is not electrically coupled to the floating gate;a second conductor extending in the first direction, being on the first level, overlapping at least the first gate, and being separated from the first conductor in the second direction, and the second conductor being electrically coupled to the second transistor; and a first via between the second conductor and the first gate, the first via electrically coupling the second conductor and the first gate together.
Liaw discloses an integrated circuit (Fig. 4C, Para. [0040]) with nfinFets and pfinFets (Para. [0032]), and multiple conductive portions on a different level overlapping the gates of the fets (Fig. 4c, Para. [0037]).
It would have been obvious to one skilled in the art before the effective filing date of the
claimed invention to add conductive portions on a different level and connect them to the gate, source and drain portions as disclosed by Liaw. The idea of connection power and signal lines is already disclosed in Bowers (Para. [0034]) and the use of perpendicular connecting structures on a different level from the gate/source/drain regions is disclosed in Liaw. Combining them in the manner described in the first claim would be obvious to a person of ordinary skill in the art, as this is a common way to connect power/signal lines to the gates/source/drains of the various transistors.
Regarding Claim 22, Bowers in view of Liaw discloses the integrated circuit of Claim 21, further comprising: a first active region extending in the first direction (Bowers, Fig. 2B, regions 204a, 204b, and 204c), and being on a third level different from the first level and the second level (this is inherent in the structure of the device), the first active region being overlapped by the floating gate and the first gate (Fig. 2B), and the first active region comprising: a first region corresponding to a first source/drain region of the floating gate transistor, and being coupled to the first voltage supply (Bowers, Fig. 2B, el. 204c, Para. [0034] – which discloses that 204c is coupled to ground); a second region corresponding to a second source/drain region of the floating gate and the first transistor, and being coupled to the first voltage supply (Bowers, Fig. 2b, 204b, Para. [0034]); and a third region corresponding to a third source/drain region of the first transistor (Bowers, Fig. 2b, el. 204a), and a second active region extending in the first direction (Bowers, Fig. 2B, els. 202a, 202b, 202c), being on the third level (this is inherent in the structure of the device), and being separated from the first active region in the second direction (Fig. 2B, where the second active region is above the first active region), the second active region being overlapped by at least the first gate (Fig. 2b, where the first gate 214b overlaps the second active region), and the second active region comprising: a fourth region corresponding to a fourth source/drain region of the second transistor, and being coupled to a second voltage supply different from the first voltage supply (Bowers, Fig. 2B, el. 202b, Para. [0026], which discloses that this region is coupled to VDD); and a fifth region corresponding to a fifth source/drain region of the second transistor (Bowers, Fig. 2B, el. 202a).
Allowable Subject Matter
Claims 6-7, 8-11, and 14-18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding Claims 6-7, none of the prior art of record teaches, suggests or renders
obvious, either alone or in combination wherein the first transistor and the second transistor are part of a first inverter, and the third region and the fifth region are electrically coupled together and correspond to an output node of the first inverter.
Regarding Claims 8-11, none of the prior art of record teaches, suggests or renders
obvious, either alone or in combination a third transistor of the second type, the third transistor being adjacent to the second transistor, and being separated from the floating gate transistor in the second direction, the third transistor comprising:a second gate extending in the second direction, being separated from the floating gate in the second direction, and overlapping the second active region;wherein the third conductive portion further overlaps the first gate, and is not electrically coupled to the first gate; andwherein the second conductive portion further overlaps the second gate, and is electrically coupled to the second gate.
Regarding Claim 14, none of the prior art of record teaches, suggests or renders
obvious, either alone or in combination a third conductor extending in the first direction, being on the second level, and overlapping the first gate, and being adjacent to the first conductor;a fourth conductor extending in the first direction, being on the second level, and overlapping the floating gate, and being adjacent to the second conductor, the fourth conductor is not electrically coupled to the floating gate;a first via between the third conductor and the first gate, the first via electrically coupling the third conductor and the first gate together; anda second via between the second conductor and the fifth region, the second via electrically coupling the second conductor and the fifth region together,wherein the first transistor and the second transistor are part of a first inverter, andthe third region and the fifth region are electrically coupled together and correspond to an output node of the first inverter.
Regarding Claims 15-18, none of the prior art of record teaches, suggests or renders
obvious, either alone or in combination a third transistor of the second type, the third transistor being adjacent to the second transistor, and being separated from the floating gate transistor in the second direction, the third transistor comprising: a second gate extending in the second direction, being separated from the floating gate in the second direction, and overlapping the second active region; wherein the first conductor further overlaps the first gate, and is not electrically coupled to the first gate; and wherein the second conductor further overlaps the second gate, and is electrically coupled to the second gate.
Conclusion
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/ROHIT PARTHASARATHY/Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899
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