Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 09/15/2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Election/Restrictions
Applicant’s election of claims 1-15 and 21-25 without traverse in the reply filed on 09/15/2025 is acknowledged.
Claim Objections
Claims 5, 8 and 10 are objected to because of the following informalities:
Claim 5 is objected to for the limitation, “wherein the dielectric wall comprise a different material than the first isolation feature” as this limitation is not grammatically correct. The Examiner believes this interpretation should be read as, “wherein the dielectric wall comprises a different material than the first isolation feature”
Claim 8 is objected to for reciting the limitations, “wherein the first stack of nanosheet channel regions have a high-k dielectric layer”, “wherein the second stack of nanosheet channel regions have a high-k dielectric layer”, and “wherein the third stack of nanosheet channel regions have a high-k dielectric layer”. These limitations are objected to as they are not grammatically correct. The Examiner interprets the limitations to respectively mean, “wherein the first stack of nanosheet channel regions has a high-k dielectric layer”, “wherein the second stack of nanosheet channel regions has a high-k dielectric layer”, and “wherein the third stack of nanosheet channel regions has a high-k dielectric layer”
Claim 10 is objected to for reciting the limitation, “wherein a silicon oxide layer has a portion extending from interfacing the right surface of each of the first, second and third nanosheets to interfacing the dielectric wall” for not being in idiomatic English. The Examiner believes the limitation should recite, “wherein a silicon oxide layer has a portion which interfaces from the right surface of each of the first, second and third nanosheets to interfacing the dielectric wall”
Claim 10 is objected to for reciting the limitation, “a portion extending from interfacing the left surface of each of the fourth, fifth and sixth nanosheets to interfacing the dielectric wall” which is not in idiomatic English. The Examiner believes the limitation should recite, “a portion which interfaces from the left surface of each of the fourth, fifth and sixth nanosheets to
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 9-15 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding Claim 9,
Claim 9 recites the limitations, “wherein the high-k dielectric layer of the second gate is omitted from a portion of a fourth sidewall of each nanosheet channel region” and “wherein the high-k dielectric layer of the first gate is omitted from a portion of a fourth sidewall of each nanosheet channel region”. The Examiner finds that these limitations together are indefinite because it is not clear if the, “a portion of a fourth sidewall” is the same portion in each limitation. Because Applicant’s first gate and second gate are separate regions, the Examiner believes that there are two portions of a fourth sidewall. Therefore, the Examiner interprets the first limitation to mean, “wherein the high-k dielectric layer of the second gate is omitted from a first portion of a fourth sidewall of each nanosheet channel region” and the second limitation to mean, “wherein the high-k dielectric layer of the first gate is omitted from a second portion of a fourth sidewall of each nanosheet channel region”
Regarding Claim 10,
Claim 10 recites the limitations, “wherein a silicon oxide layer has a portion extending from interfacing the right surface of each of the first, second and third nanosheets to interfacing the dielectric wall” and “and a portion extending from interfacing the left surface of each of the fourth, fifth and sixth nanosheets to interfacing the dielectric wall”. The Examiner finds that these limitations together to be indefinite because it is not clear if “a portion” is the same portion in each limitation. Because the first, second and third nanosheets and the fourth, fifth, and sixth nanosheets belong to different nanosheet stacks, the Examiner interprets the limitations as referencing two separate portions. Therefore, the Examiner interprets the first limitation to mean, “wherein a silicon oxide layer has a first portion extending from interfacing the right surface of each of the first, second and third nanosheets to interfacing the dielectric wall” and the second limitation to mean, “and a second portion extending from interfacing the left surface of each of the fourth, fifth and sixth nanosheets to interfacing the dielectric wall”
Regarding Claims 11-15, these claims depend upon claim 10 and are therefore rejected for the same reasons.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-7 and 9 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chen et al US 20220328477 A1. Chen et al will be referenced to as Chen henceforth.
Regarding Claim 1,
Chen teaches:
“A semiconductor device (FIG. 24), comprising:
a first stack of nanosheet channel regions (annotated FIG. 24 #1) having a first gate engaging the first stack (gate electrode layer 182 (rightmost), HK dielectric layer 180 (portion surrounding the first stack of nanosheet channel regions), IL 178, [0050], [0073]);
a second stack of nanosheet channel regions (annotated FIG. 24 #1) having a second gate engaging the second stack (gate electrode layer 182 (center), HK dielectric layer 180 (portion surrounding the second stack of nanosheet channel regions) IL 178, [0050], [0073]);
a third stack of nanosheet channel regions (annotated FIG. 24 #1) having a third gate engaging the third stack (gate electrode layer 182 (leftmost), HK dielectric layer 180 (portion surrounding the third stack of nanosheet channel regions) IL 178, [0050], [0073]);
a dielectric wall disposed extending between the first gate and the second gate (dielectric layer 119, dielectric layer 128, [0048], [0068]) and
a first isolation feature disposed between the second gate and the third gate (annotated FIG. 24 #2: the first isolation feature includes dielectric features 134 and a portion of 180.); and
wherein in a first cross-sectional view (FIG. 24 is a cross-sectional view.), a sidewall of the dielectric wall interfaces a gate dielectric of the first gate and the second gate (IL 178, [0075]: 178 is made of silicon oxide and separates the gate electrode from the channel. Therefore 178 is a gate dielectric.), and wherein the first isolation feature interfaces a metal layer of the second gate (gate electrode layer 182 (center)) and a metal layer of the third gate (gate electrode layer 182 (leftmost)).”
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Regarding Claim 2,
Chen teaches:
“The semiconductor device as claimed in claim 1, wherein the dielectric wall includes a liner layer (dielectric layer 128, [0074], FIG. 24).”
Regarding Claim 3,
Chen teaches:
“The semiconductor device as claimed in claim 1, wherein the gate dielectric layer of each of the first gate, second gate and third gate is at least one of an interfacial layer or a high-k dielectric layer (IL 178, [0075]: 178 is an interfacial layer.).”
Regarding Claim 4,
Chen teaches:
“The semiconductor device as claimed in claim 1, wherein a bottommost portion of the first isolation feature is below a bottommost portion of the dielectric wall (FIG. 24: A bottommost surface of 118 is below a bottommost portion of 128.).”
Regarding Claim 5,
Chen teaches:
“The semiconductor device as claimed in claim 1, wherein the dielectric wall comprise a different material than the first isolation feature ([0048]: 119 may comprise silicon dioxide. The isolation feature comprises 180 which is made of a high-k dielectric. A high-k dielectric is defined as a dielectric with a higher dielectric constant than silicon dioxide. Therefore 180 is not silicon oxide. Therefore, the dielectric wall comprises a different material than the first isolation feature.).”
Regarding Claim 6,
Chen teaches:
“The semiconductor device as claimed in claim 1, further comprising:
a second isolation feature interfacing the first gate at a sidewall of the first gate opposing a sidewall of the first gate interfacing the dielectric wall in a cross- sectional view (annotated FIG. 25 #1: the second isolation feature interfaces the sidewall of a first gate at a first gate dielectric opposing a sidewall of the first gate interfacing the dielectric wall.).”
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Regarding Claim 7,
Chen teaches:
“The semiconductor device as claimed in claim 1, wherein the first isolation feature extends between a first source/drain feature (S/D features 160 (leftmost), [0086], FIG. 19B) and a second source/drain feature (S/D features 160 (rightmost), [0086], FIG. 19B) in another cross-sectional view (FIG. 19B: 134 stacked on 118, that is the first isolation feature, is between the leftmost and rightmost S/D features 160.).”
Regarding Claim 9,
Chen teaches:
“The semiconductor device as claimed in in claim 1 (FIG. 24), wherein the third stack of nanosheet channel regions have a high-k dielectric layer of the third gate surrounding each nanosheet channel region (HK dielectric layer 180, [0076]);
wherein the second stack of nanosheet channel regions have a high-k dielectric layer of the second gate extending on at least three sidewalls of each nanosheet channel region in a cross- sectional view (FIG. 24), wherein the high-k dielectric layer of the second gate is omitted from a portion of a fourth sidewall of each nanosheet channel region (FIG. 24), an oxide liner extending from the fourth sidewall to the dielectric wall (dielectric layers 126, [0080]); and
wherein the first stack of nanosheet channel regions have a high-k dielectric layer of the first gate extending on at least three sidewalls of each nanosheet channel region in the cross- sectional view (FIG. 24), wherein the high-k dielectric layer of the first gate is omitted from a portion of a fourth sidewall of each nanosheet channel region (FIG. 24), the oxide liner extending from the fourth sidewall to the dielectric wall (dielectric layers 126, [0080]).”
Regarding Claim 21,
Chen teaches:
“A semiconductor device, comprising:
a stack of nanosheet channel layers (annotated FIG. 24 #1: the first stack) extending in a first direction (Chen: FIG. 24: the first direction is the Y direction.);
a dielectric wall (dielectric layer 128, [0048]);
a metal gate structure (gate electrode layer 182 (rightmost), HK dielectric layer 180 (portion surrounding the first stack of nanosheet channel regions), IL 178, [0050], [0073]) including a high-k gate dielectric layer (HK dielectric layer 180 (portion surrounding the first stack of nanosheet channel regions), [0073]) and a metal layer over the high-k gate dielectric layer (gate electrode layer 182 (rightmost), [0050]), wherein the metal gate structure engages each nanosheet channel layer of the stack of nanosheet channel layers (FIG. 24: 182 electrically engages each channel layer.) and the high-k gate dielectric layer abuts the dielectric wall (FIG. 24); and an isolation feature (annotated FIG. 24 #2: the first isolation feature includes dielectric features 134 and a portion of 180.).”
Regarding Claim 22,
Chen teaches:
“The semiconductor device of claim 21, wherein the metal gate structure further includes an interfacial layer under the high-k gate dielectric layer (annotated FIG. 24 #2: the first isolation feature includes dielectric features 134 and a portion of 180.).”
Regarding Claim 23,
Chen teaches:
“The semiconductor device of claim 21, wherein the isolation feature has a bottommost surface further from the stack of nanosheet channel layers than the bottommost surface of the dielectric wall (FIG. 24: A bottommost surface of 118 is below a bottommost portion of 128.).”
Regarding Claim 24,
Chen teaches:
“The semiconductor device of claim 21, wherein the isolation feature interfaces a sidewall of the metal layer of the metal gate structure (annotated FIG. 24 #2).”
Claims 21 and 25 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by a second interpretation of Chen et al US 20220328477 A1. The second interpretation of Chen et al will be referenced to as Chen #2 henceforth.
Regarding Claim 21,
Chen #2 teaches:
“A semiconductor device, comprising:
a stack of nanosheet channel layers (annotated FIG. 24 #1: the first stack) extending in a first direction (Chen: FIG. 24: the first direction is the Y direction.);
a dielectric wall (fourth dielectric layer 136, [0057]);
a metal gate structure (gate electrode layer 182 (rightmost), HK dielectric layer 180 (portion surrounding the first stack of nanosheet channel regions), IL 178, [0050], [0073]) including a high-k gate dielectric layer (HK dielectric layer 180 (portion surrounding the first stack of nanosheet channel regions), [0073]) and a metal layer over the high-k gate dielectric layer (gate electrode layer 182 (rightmost), [0050]), wherein the metal gate structure engages each nanosheet channel layer of the stack of nanosheet channel layers (FIG. 24: 182 electrically engages each channel layer.) and the high-k gate dielectric layer abuts the dielectric wall (FIG. 24); and an isolation feature (fifth dielectric layer 138, [0057], annotated FIG. 24 #5: The isolation feature is the rightmost 138 in FIG. 24.).”
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Regarding Claim 25,
Chen #2 teaches:
“The semiconductor device in claim 21, further comprising:
another isolation feature extending through the dielectric wall (dielectric layer 138 (the one passing through 136 in the middle of FIG. 24), [0057], FIG. 24), wherein a bottom surface of the another isolation feature and a bottom surface of the isolation feature are coplanar in a cross-sectional view (FIG. 24).”
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 8 and 10-15 are rejected under 35 U.S.C. 103 as being unpatentable over Chen as applied to claims 1-7 and 9 above, and further in view of Mishra et al US 20220093474 A1. Mishra et al will be referenced to as Mishra henceforth.
Regarding Claim 8,
Chen teaches:
“The semiconductor device as claimed in claim 1 (FIG. 24),”
Chen doesn’t substantially teach:
“wherein the first stack of nanosheet channel regions have a high-k dielectric layer of the first gate surrounding each nanosheet channel region of the first stack of nanosheet channel regions;
wherein the second stack of nanosheet channel regions have a high-k dielectric layer of the second gate surrounding each nanosheet channel region of the second stack of nanosheet channel regions; and
wherein the third stack of nanosheet channel regions have a high-k dielectric layer of the third gate surrounding each nanosheet channel region of the third stack of nanosheet channel regions.”
However, Mishra teaches:
“wherein the first stack of nanosheet channel regions have a high-k dielectric layer of the first gate surrounding each nanosheet channel region of the first stack of nanosheet channel regions (Mishra: gate dielectric material 348, first face 422-1, second face 422-2, first sidewall 424-1, second sidewall 424-2, [0059], FIG. 4A: 422-1, 422-2, 424-1, and 424-2 each consist of gate dielectric material 348 and surround the channels.);
wherein the second stack of nanosheet channel regions have a high-k dielectric layer of the second gate surrounding each nanosheet channel region of the second stack of nanosheet channel regions (Mishra: gate dielectric material 348, first face 422-1, second face 422-2, first sidewall 424-1, second sidewall 424-2, [0059], FIG. 4A: 422-1, 422-2, 424-1, and 424-2 each consist of gate dielectric material 348 and surround the channels.); and
wherein the third stack of nanosheet channel regions have a high-k dielectric layer of the third gate surrounding each nanosheet channel region of the third stack of nanosheet channel regions (Mishra: gate dielectric material 348, first face 422-1, second face 422-2, first sidewall 424-1, second sidewall 424-2, [0059], FIG. 4A: 422-1, 422-2, 424-1, and 424-2 each consist of gate dielectric material 348 and surround the channels.).”
It would have been obvious to one with ordinary skill in the art before the effective filing
date of the invention to recognize that the device of Chen is modifiable in view of Mishra by fully wrapping the gate dielectric of Mishra around the channels of Chen.
This is because Chen teaches a gate dielectric partially surrounding a channel. Chen doesn’t substantively teach a gate dielectric completely surrounding a channel. Mishra teaches a gate dielectric partially surrounding a channel. Mishra further teaches a gate dielectric fully surrounding a channel and connected to a dielectric wall. Because both Chen and Mishra have a gate dielectric partially surrounding a channel, one of ordinary skill in the art would have deemed it obvious to substitute the gate dielectric partially surrounding a channel of Chen for a gate dielectric fully surrounding a channel and connected to a dielectric wall of Mishra for the predictable result of insulating a channel from a gate electrode.
Regarding Claim 10,
Chen teaches:
“A semiconductor device (Chen: FIG. 24), comprising:
a first vertical stack of nanosheet channel regions (Chen: annotated FIG. 24 #1), wherein the first vertical stack includes a first nanosheet (Chen: annotated FIG. 24 #3), a second nanosheet above the first nanosheet (Chen: annotated FIG. 24 #3) a second vertical stack of nanosheet channel regions spaced a distance from the first vertical stack (Chen: annotated FIG. 24 #1), wherein the second vertical stack includes a fourth nanosheet (Chen: annotated FIG. 24 #3), a fifth nanosheet above the fourth nanosheet (Chen: annotated FIG. 24 #3) a dielectric wall in the distance (Chen: dielectric layer 119, dielectric layer 128, [0048], [0068]), wherein a silicon oxide layer has a portion extending from interfacing the right surface of each of the first, second and third nanosheets to interfacing the dielectric wall (Chen: IL 178, [0075]: 178 is made of silicon oxide and separates the gate electrode from the channel. Therefore 178 is a gate dielectric.) and a portion extending from interfacing the left surface of each of the fourth, fifth and sixth nanosheets to interfacing the dielectric wall (Chen: FIG. 24), and the high-k dielectric layer is formed on the silicon oxide layer (Chen: FIG. 24).”
Chen doesn’t substantially teach alone:
“and a third nanosheet above the second nanosheet, wherein each of the first, second and third nanosheets is defined by an upper surface, a left surface, a right surface, and a bottom surface in a cross-sectional view; and a sixth nanosheet above the fifth nanosheet wherein each of the fourth, fifth and sixth nanosheets is defined by an upper surface, a left surface, a right surface, and a bottom surface in the cross-sectional view;
and wherein a high-k dielectric layer is formed on each of the upper surface, lower surface and left surface of each of the first, second and third nanosheets, and the high-k dielectric layer is formed on each of the upper surface, lower surface and right surface of each of the fourth, fifth and sixth nanosheets, ”
However, Chen/Mishra teaches:
“and a third nanosheet above the second nanosheet (Chen/Mishra: Mishra: FIG. 4A: a third nanosheet is above a second nanosheet which is above a first nanosheet. One of ordinary skill in the art would include a third nanosheet above a second nanosheet because it would increase the amount of current and therefore operation speed is improved.), wherein each of the first, second and third nanosheets is defined by an upper surface, a left surface, a right surface, and a bottom surface in a cross-sectional view (Chen/Mishra: Chen: FIG. 24; Mishra: FIG. 4A: Each nanosheet has an upper surface, a left surface, a right surface, and a bottom surface in a cross-sectional view.); and a sixth nanosheet above the fifth nanosheet (Chen/Mishra: Mishra: FIG. 4A: a third nanosheet is above a second nanosheet which is above a first nanosheet. One of ordinary skill in the art would include a third nanosheet above a second nanosheet because it would increase the amount of current and therefore operation speed is improved.) wherein each of the fourth, fifth and sixth nanosheets is defined by an upper surface, a left surface, a right surface, and a bottom surface in the cross-sectional view (Chen/Mishra: Chen: FIG. 24; Mishra: FIG. 4A: Each nanosheet has an upper surface, a left surface, a right surface, and a bottom surface in a cross-sectional view.);
and wherein a high-k dielectric layer is formed on each of the upper surface, lower surface and left surface of each of the first, second and third nanosheets (Chen/Mishra: Chen: HK dielectric layer 180, [0076]; Mishra: gate dielectric material 348, first face 422-1, second face 422-2, first sidewall 424-1, second sidewall 424-2, [0059], FIG. 4A: 422-1, 422-2, 424-1, and 424-2 each consist of gate dielectric material 348 and surround the channels. The gate dielectric fully surrounds the channel layers.), and the high-k dielectric layer is formed on each of the upper surface, lower surface and right surface of each of the fourth, fifth and sixth nanosheets (Chen/Mishra: Chen: HK dielectric layer 180, [0076]; Mishra: gate dielectric material 348, first face 422-1, second face 422-2, first sidewall 424-1, second sidewall 424-2, [0059], FIG. 4A: 422-1, 422-2, 424-1, and 424-2 each consist of gate dielectric material 348 and surround the channels. The gate dielectric fully surrounds the channel layers.), “
It would have been obvious to one with ordinary skill in the art before the effective filing
date of the invention to recognize that the device of Chen is modifiable in view of Mishra by incorporating an additional channel into the first and second nanosheet stacks.
This is because one of ordinary skill in the art would recognize that an additional nanosheet in the first and second vertical stacks increases the amount of current passing through the transistor which therefore increases operating speeds of the transistor device.
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Regarding Claim 12,
Chen/Mishra teaches:
“The semiconductor device of claim 11, wherein the high-k dielectric layer directly interfaces the dielectric wall (FIG. 24).”
Regarding Claim 13,
Chen/Mishra teaches:
“The semiconductor device of claim 10, wherein portions of the silicon oxide layer extending from the right surface of each of the first, second and third nanosheets extend less than or equal to about 6 nanometers (Chen: [0061], [0075], FIG. 22: Note: [0075] states "The thickness of the IL 148 is chosen... the IL 148 has a thickness ranging from about 0.5 nm to about 2 nm" in the context of FIG. 22. There is no IL 148, so the element is either IL 178 or mask structure 148. Given that no element 148 is shown in FIG. 22, the mask structure 148 is shown in other embodiments, and the repeated reference to IL 178 earlier in the paragraph, it's clear this should read IL 178. Therefore 178 has a thickness from 0.5 nm to about 2nm. This range lies within 0 nm to 6 nm.).”
Claims 10-11 and 14-15 are rejected under 35 U.S.C. 103 as being unpatentable over another interpretation of Chen #3 in view of Mishra.
Regarding Claim 10,
Chen #3 teaches:
“A semiconductor device (Chen #3: FIG. 24), comprising:
a first vertical stack of nanosheet channel regions (Chen #3: annotated FIG. 24 #1), wherein the first vertical stack includes a first nanosheet (Chen #3: annotated FIG. 24 #3), a second nanosheet above the first nanosheet (Chen #3: annotated FIG. 24 #3) a second vertical stack of nanosheet channel regions spaced a distance from the first vertical stack (Chen #3: annotated FIG. 24 #1), wherein the second vertical stack includes a fourth nanosheet (Chen #3: annotated FIG. 24 #3), a fifth nanosheet above the fourth nanosheet (Chen #3: annotated FIG. 24 #3) a dielectric wall in the distance (Chen #3: dielectric layer 119, dielectric layer 128, [0048], [0068]), wherein a silicon oxide layer has a portion extending from interfacing the right surface of each of the first, second and third nanosheets to interfacing the dielectric wall (Chen #3: first dielectric layer 126, [0048], FIG. 24) and a portion extending from interfacing the left surface of each of the fourth, fifth and sixth nanosheets to interfacing the dielectric wall (Chen #3: FIG. 24), and wherein a high-k dielectric layer is formed on each of the upper surface, lower surface and left surface of each of the first, second and third nanosheets (Chen #3/Mishra: Chen #3: HK dielectric layer 180, [0076]; Mishra: gate dielectric material 348, first face 422-1, second face 422-2, first sidewall 424-1, second sidewall 424-2, [0059], FIG. 4A: 422-1, 422-2, 424-1, and 424-2 each consist of gate dielectric material 348 and surround the channels. The gate dielectric fully surrounds the channel layers.) and the high-k dielectric layer is formed on the silicon oxide layer (Chen #3: FIG. 24).”
Chen #3 doesn’t substantially teach alone:
“and a third nanosheet above the second nanosheet, wherein each of the first, second and third nanosheets is defined by an upper surface, a left surface, a right surface, and a bottom surface in a cross-sectional view; and a sixth nanosheet above the fifth nanosheet wherein each of the fourth, fifth and sixth nanosheets is defined by an upper surface, a left surface, a right surface, and a bottom surface in the cross-sectional view; and the high-k dielectric layer is formed on each of the upper surface, lower surface and right surface of each of the fourth, fifth and sixth nanosheets,”
However, Mishra teaches:
“and a third nanosheet above the second nanosheet (Chen #3/Mishra: Mishra: FIG. 4A: a third nanosheet is above a second nanosheet which is above a first nanosheet. One of ordinary skill in the art would include a third nanosheet above a second nanosheet would increase the amount of current and therefore operation speed is improved.), wherein each of the first, second and third nanosheets is defined by an upper surface, a left surface, a right surface, and a bottom surface in a cross-sectional view (Chen #3/Mishra: Chen #3: FIG. 24; Mishra: FIG. 4A: Each nanosheet has an upper surface, a left surface, a right surface, and a bottom surface in a cross-sectional view.); and a sixth nanosheet above the fifth nanosheet (Chen #3/Mishra: Mishra: FIG. 4A: a third nanosheet is above a second nanosheet which is above a first nanosheet. One of ordinary skill in the art would include a third nanosheet above a second nanosheet would increase the amount of current and therefore operation speed is improved.) wherein each of the fourth, fifth and sixth nanosheets is defined by an upper surface, a left surface, a right surface, and a bottom surface in the cross-sectional view (Chen #3/Mishra: Chen #3: FIG. 24; Mishra: FIG. 4A: Each nanosheet has an upper surface, a left surface, a right surface, and a bottom surface in a cross-sectional view.); and the high-k dielectric layer is formed on each of the upper surface, lower surface and right surface of each of the fourth, fifth and sixth nanosheets (Chen #3: /Mishra: Chen #3: HK dielectric layer 180, [0076]; Mishra: gate dielectric material 348, first face 422-1, second face 422-2, first sidewall 424-1, second sidewall 424-2, [0059], FIG. 4A: 422-1, 422-2, 424-1, and 424-2 each consist of gate dielectric material 348 and surround the channels. The gate dielectric fully surrounds the channel layers.),”
It would have been obvious to one with ordinary skill in the art before the effective filing
date of the invention to recognize that the device of Chen #3 is modifiable in view of Mishra by incorporating an additional channel into the first and second nanosheet stacks.
This is because one of ordinary skill in the art would recognize that an additional nanosheet in the first and second vertical stacks increases the amount of current passing through the transistor which therefore increases operating speeds of the transistor device.
Regarding Claim 11,
Chen #3/Mishra teaches:
“The semiconductor device of claim 10, wherein the high-k dielectric layer directly interfaces the silicon oxide layer (Chen #3: FIG. 24). ”
Regarding Claim 14,
Chen #3/Mishra teaches:
“The semiconductor device of claim 10, wherein an interfacial layer interposes the high-k dielectric layer and each of the upper surface, lower surface and left surface of each of the first, second and third nanosheets (Chen #3/Mishra: Chen #3: IL 178, [0075] annotated FIG. 24 #4:178 is between 180 and the left surface of the channel at the indicated portions. The same is true for a third channel layer which is not illustrated.), and the interfacial layer interposes the high-k dielectric layer and each of the upper surface, lower surface and right surface of each of the fourth, fifth and sixth nanosheets (Chen #3/Mishra: Chen #3: IL 178, [0075] annotated FIG. 24 #4:178 is between 180 and the right surface of the channel at the indicated portions. The same is true for a third channel layer which is not illustrated.).”
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Regarding Claim 15,
Chen #3/Mishra teaches:
“The semiconductor device of claim 14, wherein the interfacial layer interfaces the silicon oxide layer (Chen #3: FIG. 24).”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALEXANDRE XAVIER RAMIREZ whose telephone number is (571)272-2715. The examiner can normally be reached Monday - Friday 8:30 AM to 6:00 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Partridge can be reached at (571) 270-1402. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ALEXANDRE X RAMIREZ/Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812
Prosecution Insights