DETAILED ACTION
The present application is being examined under the pre-AIA first to invent provisions.
Claim Objections
Claims 1, 14, 15 and 20 are objected to because of the following informalities:
Claim 1 recites the limitation “said first memory cells” and “said second memory cells” in lines 13-14.
However, there is lack of proper antecedent basis for “said memory cells” and in the claim. Changing “said first memory cells” and “said second memory cells” to --said plurality of first memory cells-- and -- said plurality of second memory cells-- in the claim provides proper antecedent basis.
Claim 14 recites the limitation “said devices” in line 2. However, there is a lack of proper antecedent basis for “said devices” in the claim. Changing “said devices” to --said 3D semiconductor device-- provides proper antecedent basis.
Claim 15 recites the limitation “wherein said memory control circuits comprise control of data written into said first memory cells and into said second memory cells” in lines 14-15.
However, there is a lack of proper antecedent basis for “said first memory cells” and “said second memory cells” in the claim. Changing “said first memory cells” and “said second memory cells” to -- said plurality of first memory cells-- and --said plurality of second memory cells-- provides proper antecedent basis.
Claim 20 recites the limitation “said devices” in line 2. However, there is a lack of proper antecedent basis for “said devices” in the claim. Changing “said devices” to --said 3D semiconductor device-- provides proper antecedent basis.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-7, 12 and 18 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation “wherein at least one of said transistors comprises a hafnium oxide gate dielectric”
However, there is lack of proper antecedent basis for “said transistors” because it is not clear which transistors being claimed. Is it “first transistors” being recited? Is it “second transistors” being recited? Is it “third transistors” being recited? And is it “fourth transistors” being recited?
Hence, there is a great deal of ambiguity the which transistor comprised HfO gate dielectric. Therefore, the claim lacks clarity in the scope and meaning.
Claim 5 recites the limitation “wherein said memory cells are DRAM type memory cells” in line 2.
However, there is a lack of clarity that which memory cells are DRAM type memory cells.
Is it the plurality of first memory cells are being DRAM type memory cells? Is it the plurality of second memory cells are being DRAM type memory cells? Or both?
Therefore, the claim lacks clarity in the meaning and scope.
Claims 2-7 are also rejected as being dependent of the rejected claim 1.
Claim 12 recites the limitation “wherein said memory cells are DRAM type memory cells” in line 2.
However, there is a lack of clarity that which memory cells are DRAM type memory cells.
Is it the plurality of first memory cells are being DRAM type memory cells? Is it the plurality of second memory cells are being DRAM type memory cells? Or both?
Claim 18 recites the limitation “wherein said memory cells are DRAM type memory cells” in line 2.
However, there is a lack of clarity that which memory cells are DRAM type memory cells.
Is it the plurality of first memory cells are being DRAM type memory cells? Is it the plurality of second memory cells are being DRAM type memory cells? Or both?
Applicant’s cooperation is requested in reviewing the claims’ structure to ensure proper claim construction and to correct any subsequently discovered instances of claim language noncompliance. See Morton International Inc., 28USPQ2d 1190, 1195 (CAFC, 1993).
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims of U.S. Patent No.12,469,735. Although the claims at issue are not identical, they are not patentably distinct from each other because of the followings:
Although the conflicting claims are not identical, the scope of the claimed limitations of the instant application as claimed in claims 1-20 is similar to that of the claimed limitations of U.S. Patent No. 12,469,735 as claimed in claims 1-20. Therefore, the claims are not patentably distinct from each other.
The instant application:
1. A method of fabricating a 3D semiconductor device, the method comprising: forming a first level comprising a first single crystal layer, wherein said first level comprises first transistors, and wherein each of said first transistors comprises a single crystal channel; forming a first metal layer in said first level; forming a second metal layer overlaying said first metal layer; forming memory control circuits in said first level; forming a second level comprising a plurality of second transistors, wherein at least one of said plurality of second transistors comprises a metal gate; forming a third level comprising a plurality of third transistors; and forming a fourth level comprising a plurality of fourth transistors, wherein said second level comprises a plurality of first memory cells, wherein said fourth level comprises a plurality of second memory cells, wherein said memory control circuits comprise control of data written into said first memory cells and into said second memory cells, and wherein at least one of said transistors comprises a hafnium oxide gate dielectric.
2. The method according to claim 1, further comprising: forming metal pads and metal pins for connecting said second level to said first level.
3. The method according to claim 1, further comprising: fabricating at least one Phase-Lock-Loop ("PLL") circuit or at least one Digital-Lock-Loop ("DLL") circuit.
4. The method according to claim 1, further comprising: forming a plurality of Through Silicon Vias ("TSVs") in said first level.
5. The method according to claim 1, wherein said memory cells are DRAM type memory cells.
6. The method according to claim 1, further comprising: configuring at least one of said first transistors to control power delivery for at least one of said plurality of third transistors.
7. The method according to claim 1, further comprising: forming pads for connecting inputs and outputs of said device to an external device, wherein said pads are disposed underneath said first single crystal layer.
8. A method of fabricating a 3D semiconductor device, the method comprising: forming a first level comprising a first single crystal layer, wherein said first level comprises first transistors, and wherein each of said first transistors comprises a single crystal channel; forming a first metal layer in said first level; forming a second metal layer overlaying said first metal layer; forming memory control circuits in said first level; forming a second level comprising a plurality of second transistors, wherein at least one of said plurality of second transistors comprises a metal gate; forming a third level comprising a plurality of third transistors; forming a fourth level comprising a plurality of fourth transistors, wherein said second level comprises a plurality of first memory cells, wherein said fourth level comprises a plurality of second memory cells; bonding said second level to said first level, wherein said memory control circuits comprise control of data written into said plurality of first memory cells and into said plurality of second memory cells; and further comprising: forming a plurality of Through Silicon Vias ("TSVs") in said first level.
9. The method according to claim 8, further comprising: forming metal pads and metal pins for connecting said second level to said first level.
10. The method according to claim 8, further comprising: fabricating at least one Phase-Lock-Loop ("PLL") circuit or at least one Digital-Lock-Loop ("DLL") circuit.
11. The method according to claim 8, wherein at least one of said transistors comprises a hafnium oxide gate dielectric.
12. The method according to claim 8, wherein said memory cells are DRAM type memory cells.
13. The method according to claim 8, further comprising: configuring at least one of said first transistors to control power delivery for at least one of said plurality of third transistors.
14. The method according to claim 8, further comprising: forming pads for connecting inputs and outputs of said device to an external device, wherein said pads are disposed underneath said first single crystal layer.
15. A method of fabricating a 3D semiconductor device, the method comprising: forming a first level comprising a first single crystal layer, wherein said first level comprises first transistors, and wherein each of said first transistors comprises a single crystal channel; forming a first metal layer in said first level; forming a second metal layer overlaying said first metal layer; forming memory control circuits in said first level; forming a second level comprising a plurality of second transistors, wherein at least one of said plurality of second transistors comprises a metal gate; forming a third level comprising a plurality of third transistors; forming a fourth level comprising a plurality of fourth transistors, wherein said second level comprises a plurality of first memory cells, wherein said fourth level comprises a plurality of second memory cells, wherein said memory control circuits comprise control of data written into said first memory cells and into said second memory cells, and wherein said first level comprises at least one Phase-Lock-Loop ("PLL") circuit or at least one Digital-Lock-Loop ("DLL") circuit.
16. The method according to claim 15, further comprising: forming metal pads and metal pins for connecting said second level to said first level.
17. The method according to claim 15, further comprising: forming a plurality of Through Silicon Vias ("TSVs") in said first level
18. The method according to claim 15, wherein said memory cells are DRAM type memory cells.
19. The method according to claim 15, further comprising: configuring at least one of said first transistors to control power delivery for at least one of said plurality of third transistors.
20. The method according to claim 15, further comprising: forming pads for connecting inputs and outputs of said device to an external device, wherein said pads are disposed underneath said first single crystal layer.
U.S. Patent No. 12,469,735:
1. A 3D semiconductor device, the device comprising: a first level comprising a first single crystal layer, said first level comprising first transistors, wherein each of said first transistors comprises a single crystal channel; a first metal layer; a second metal layer overlaying said first metal layer; a second level comprising a plurality of second transistors, said second level overlaying said first level; a third level comprising a plurality of third transistors, said third level overlaying said second level; a fourth level comprising a plurality of fourth transistors, said fourth level overlaying said third level, wherein said second level comprises a plurality of first memory cells, wherein each of said plurality of first memory cells comprises at least one of said second transistors, wherein said fourth level comprises a plurality of second memory cells, wherein each of said plurality of second memory cells comprises at least one of said fourth transistors, wherein said first level comprises memory control circuits, wherein at least one of said second transistors comprises a metal gate, wherein said memory control circuits control writing to said plurality of second memory cells, and wherein at least one of said second transistors comprises a hafnium oxide gate dielectric.
2. The device according to claim 1, further comprising: metal pads and metal pins for connecting said second level to said first level.
3. The device according to claim 1, further comprising: at least one Phase-Lock-Loop ("PLL") circuit or at least one Digital-Lock-Loop ("DLL") circuit.
4. The device according to claim 1, wherein said first level comprises a plurality of Through Silicon Via ("TSV").
5. The device according to claim 1, wherein said memory cells are DRAM type memory cells.
6. The device according to claim 1, wherein at least one of said first transistors controls power delivery for at least one of said third transistors.
7. The device according to claim 1, further comprising: pads for connecting inputs and outputs of said device to an external device, wherein said pads are disposed underneath said first single crystal layer.
8. A 3D semiconductor device, the device comprising: a first level comprising a first single crystal layer, said first level comprising first transistors, wherein each of said first transistors comprises a single crystal channel; a first metal layer; a second metal layer overlaying said first metal layer; a second level comprising a plurality of second transistors, said second level overlaying said first level; a third level comprising a plurality of third transistors, said third level overlaying said second level; a fourth level comprising a plurality of fourth transistors, said fourth level overlaying said third level, wherein said second level comprises a plurality of first memory cells, wherein each of said plurality of first memory cells comprises at least one of said second transistors, wherein said fourth level comprises a plurality of second memory cells, wherein each of said plurality of second memory cells comprises at least one of said fourth transistors, wherein said first level comprises memory control circuits, wherein at least one of said second transistors comprises a metal gate, wherein said memory control circuits control writing to said plurality of second memory cells, and wherein said first level comprises a plurality of Through Silicon Via ("TSV").
9. The device according to claim 8, further comprising: metal pads and metal pins for connecting said second level to said first level.
10. The device according to claim 8, further comprising: at least one Phase-Lock-Loop ("PLL") circuit or at least one Digital-Lock-Loop ("DLL") circuit.
11. The device according to claim 8, wherein said third level comprises at least four independently controlled memory arrays.
12. The device according to claim 8, wherein said memory cells are DRAM type memory cells.
13. The device according to claim 8, wherein at least one of said first transistors controls power delivery for at least one of said third transistors.
14. The device according to claim 8, further comprising: pads for connecting inputs and outputs of said device to an external device, wherein said pads are disposed underneath said first single crystal layer.
15. A 3D semiconductor device, the device comprising: a first level comprising a first single crystal layer, said first level comprising first transistors, wherein each of said first transistors comprises a single crystal channel; a first metal layer; a second metal layer overlaying said first metal layer; a second level comprising a plurality of second transistors, said second level overlaying said first level; a third level comprising a plurality of third transistors, said third level overlaying said second level; and a fourth level comprising a plurality of fourth transistors, said fourth level overlaying said third level, wherein said second level comprises a plurality of first memory cells, wherein each of said plurality of first memory cells comprises at least one of said second transistors, wherein said fourth level comprises a plurality of second memory cells, wherein each of said plurality of second memory cells comprises at least one of said fourth transistors, wherein said first level comprises memory control circuits, wherein at least one of said second transistors comprises a metal gate, wherein said memory control circuits control reading from said plurality of second memory cells, wherein said memory control circuits control writing to said plurality of third memory cells, and wherein said first level is bonded to said second level.
17. The device according to claim 15, further comprising: at least one Phase-Lock-Loop ("PLL") circuit or at least one Digital-Lock-Loop ("DLL") circuit.
16. The device according to claim 15, further comprising: metal pads and metal pins for connecting said second level to said first level.
20. The device according to claim 15, wherein said first level comprises a plurality of Through Silicon Via ("TSV").
18. The device according to claim 15, wherein said memory cells are DRAM type memory cells.
19. The device according to claim 15, wherein at least one of said first transistors controls power delivery for at least one of said third transistors.
7. The device according to claim 1, further comprising: pads for connecting inputs and outputs of said device to an external device, wherein said pads are disposed underneath said first single crystal layer.
Claims 8-10 and 12-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims of U.S. Patent No.12,125,737. Although the claims at issue are not identical, they are not patentably distinct from each other because of the followings:
Although the conflicting claims are not identical, the scope of the claimed limitations of the instant application as claimed in claims 8-10 and 12-20 is similar to that of the claimed limitations of U.S. Patent No. 12,125,737 as claimed in claims 8-20. Therefore, the claims are not patentably distinct from each other.
The instant application:
8. A method of fabricating a 3D semiconductor device, the method comprising: forming a first level comprising a first single crystal layer, wherein said first level comprises first transistors, and wherein each of said first transistors comprises a single crystal channel; forming a first metal layer in said first level; forming a second metal layer overlaying said first metal layer; forming memory control circuits in said first level; forming a second level comprising a plurality of second transistors, wherein at least one of said plurality of second transistors comprises a metal gate; forming a third level comprising a plurality of third transistors; forming a fourth level comprising a plurality of fourth transistors, wherein said second level comprises a plurality of first memory cells, wherein said fourth level comprises a plurality of second memory cells; bonding said second level to said first level, wherein said memory control circuits comprise control of data written into said plurality of first memory cells and into said plurality of second memory cells; and further comprising: forming a plurality of Through Silicon Vias ("TSVs") in said first level.
9. The method according to claim 8, further comprising: forming metal pads and metal pins for connecting said second level to said first level.
10. The method according to claim 8, further comprising: fabricating at least one Phase-Lock-Loop ("PLL") circuit or at least one Digital-Lock-Loop ("DLL") circuit.
12. The method according to claim 8, wherein said memory cells are DRAM type memory cells.
13. The method according to claim 8, further comprising: configuring at least one of said first transistors to control power delivery for at least one of said plurality of third transistors.
14. The method according to claim 8, further comprising: forming pads for connecting inputs and outputs of said device to an external device, wherein said pads are disposed underneath said first single crystal layer.
15. A method of fabricating a 3D semiconductor device, the method comprising: forming a first level comprising a first single crystal layer, wherein said first level comprises first transistors, and wherein each of said first transistors comprises a single crystal channel; forming a first metal layer in said first level; forming a second metal layer overlaying said first metal layer; forming memory control circuits in said first level; forming a second level comprising a plurality of second transistors, wherein at least one of said plurality of second transistors comprises a metal gate; forming a third level comprising a plurality of third transistors; forming a fourth level comprising a plurality of fourth transistors, wherein said second level comprises a plurality of first memory cells, wherein said fourth level comprises a plurality of second memory cells, wherein said memory control circuits comprise control of data written into said first memory cells and into said second memory cells, and wherein said first level comprises at least one Phase-Lock-Loop ("PLL") circuit or at least one Digital-Lock-Loop ("DLL") circuit.
17. The method according to claim 15, further comprising: forming a plurality of Through Silicon Vias ("TSVs") in said first level
16. The method according to claim 15, further comprising: forming metal pads and metal pins for connecting said second level to said first level.
18. The method according to claim 15, wherein said memory cells are DRAM type memory cells.
19. The method according to claim 15, further comprising: configuring at least one of said first transistors to control power delivery for at least one of said plurality of third transistors.
20. The method according to claim 15, further comprising: forming pads for connecting inputs and outputs of said device to an external device, wherein said pads are disposed underneath said first single crystal layer.
U.S. Patent No. 12,125,737:
8. A 3D semiconductor device, the device comprising: a first level comprising a first single crystal layer, said first level comprising first transistors, wherein each of said first transistors comprises a single crystal channel; a first metal layer; a second metal layer overlaying said first metal layer; a second level comprising a plurality of second transistors, said second level overlaying said first level; a third level comprising a plurality of third transistors, said third level overlaying said second level; a fourth level comprising a plurality of fourth transistors, said fourth level overlaying said third level, wherein said second level comprises a plurality of first memory cells, wherein each of said plurality of first memory cells comprises at least one of said second transistors, wherein said fourth level comprises a plurality of second memory cells, wherein each of said plurality of second memory cells comprises at least one of said fourth transistors, wherein said first level comprises memory control circuits, and wherein said memory control circuits control writing to said plurality of second memory cells; and a plurality of Serializer and Deserializer ("SerDes") circuits.
11. The device according to claim 8, wherein said first level comprises a plurality of Through Silicon Via ("TSV").
9. The device according to claim 8, further comprising: metal pads and metal pins for connecting said second level to said first level.
10. The device according to claim 8, further comprising: at least one Phase-Lock-Loop ("PLL") circuit or at least one Digital-Lock-Loop ("DLL") circuit.
12. The device according to claim 8, wherein said memory cells are DRAM type memory cells.
13. The device according to claim 8, wherein at least one of said first transistors controls power delivery for at least one of said third transistors.
14. The device according to claim 8, further comprising: pads for connecting inputs and outputs of said device to an external device, wherein said pads are disposed underneath said first single crystal layer.
15. A 3D semiconductor device, the device comprising: a first level comprising a first single crystal layer, said first level comprising first transistors, wherein each of said first transistors comprises a single crystal channel; a first metal layer; a second metal layer overlaying said first metal layer; a second level comprising a plurality of second transistors, said second level overlaying said first level; a third level comprising a plurality of third transistors, said third level overlaying said second level; and a fourth level comprising a plurality of fourth transistors, said fourth level overlaying said third level, wherein said second level comprises a plurality of first memory cells, wherein each of said plurality of first memory cells comprises at least one of said second transistors, wherein said fourth level comprises a plurality of second memory cells, wherein each of said plurality of second memory cells comprises at least one of said fourth transistors, wherein said first level comprises memory control circuits, wherein said memory control circuits control writing to said plurality of second memory cells, and wherein said first level comprises a plurality of Through Silicon Via ("TSV").
17. The device according to claim 15, further comprising: at least one Phase-Lock-Loop ("PLL") circuit or at least one Digital-Lock-Loop ("DLL") circuit.
16. The device according to claim 15, further comprising: metal pads and metal pins for connecting said second level to said first level.
18. The device according to claim 15, wherein said memory cells are DRAM type memory cells.
19. The device according to claim 15, wherein at least one of said first transistors controls power delivery for at least one of said third transistors.
20. The device according to claim 15, further comprising: pads for connecting inputs and outputs of said device to an external device, wherein said pads are disposed underneath said first single crystal layer.
Claims 1-7 and 11 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1-7 of U.S. Patent No. 12,125,737 in view of Brask et al. (US 2007/0001173).
The instant application:
1. A method of fabricating a 3D semiconductor device, the method comprising: forming a first level comprising a first single crystal layer, wherein said first level comprises first transistors, and wherein each of said first transistors comprises a single crystal channel; forming a first metal layer in said first level; forming a second metal layer overlaying said first metal layer; forming memory control circuits in said first level; forming a second level comprising a plurality of second transistors, wherein at least one of said plurality of second transistors comprises a metal gate; forming a third level comprising a plurality of third transistors; and forming a fourth level comprising a plurality of fourth transistors, wherein said second level comprises a plurality of first memory cells, wherein said fourth level comprises a plurality of second memory cells, wherein said memory control circuits comprise control of data written into said first memory cells and into said second memory cells, and wherein at least one of said transistors comprises a hafnium oxide gate dielectric.
3. The method according to claim 1, further comprising: fabricating at least one Phase-Lock-Loop ("PLL") circuit or at least one Digital-Lock-Loop ("DLL") circuit.
2. The method according to claim 1, further comprising: forming metal pads and metal pins for connecting said second level to said first level.
4. The method according to claim 1, further comprising: forming a plurality of Through Silicon Vias ("TSVs") in said first level.
5. The method according to claim 1, wherein said memory cells are DRAM type memory cells.
6. The method according to claim 1, further comprising: configuring at least one of said first transistors to control power delivery for at least one of said plurality of third transistors.
7. The method according to claim 1, further comprising: forming pads for connecting inputs and outputs of said device to an external device, wherein said pads are disposed underneath said first single crystal layer.
11. The method according to claim 8, wherein at least one of said transistors comprises a hafnium oxide gate dielectric.
U.S. Patent No. 12,125,737:
1. A 3D semiconductor device, the device comprising: a first level comprising a first single crystal layer, said first level comprising first transistors, wherein each of said first transistors comprises a single crystal channel; a first metal layer; a second metal layer overlaying said first metal layer; a second level comprising a plurality of second transistors, said second level overlaying said first level; a third level comprising a plurality of third transistors, said third level overlaying said second level; a fourth level comprising a plurality of fourth transistors, said fourth level overlaying said third level, wherein said second level comprises a plurality of first memory cells, wherein each of said plurality of first memory cells comprises at least one of said second transistors, wherein said fourth level comprises a plurality of second memory cells, wherein each of said plurality of second memory cells comprises at least one of said fourth transistors, wherein said first level comprises memory control circuits, and wherein said memory control circuits control writing to said plurality of second memory cells; and at least one Phase-Lock-Loop ("PLL") circuit or at least one Digital-Lock-Loop ("DLL") circuit.
2. The device according to claim 1, further comprising: metal pads and metal pins for connecting said second level to said first level.
4. The device according to claim 1, wherein said first level comprises a plurality of Through Silicon Via ("TSV").
5. The device according to claim 1, wherein said memory cells are DRAM type memory cells.
6. The device according to claim 1, wherein at least one of said first transistors controls power delivery for at least one of said third transistors.
7. The device according to claim 1, further comprising: pads for connecting inputs and outputs of said device to an external device, wherein said pads are disposed underneath said first single crystal layer.
Although it is well-known in the art use of HfO2 (hafnium oxide) gate dielectric layer for its excellent thermal stability and high dielectric constant which effectively reduces gate leakage current, U.S. Patent No. 12,125,737 does not claim that wherein at least one of said transistors comprises a hafnium oxide gate dielectric.
Brask et al. disclose semiconductor device comprises high dielectric constant hafnium oxide gate dielectric (250). See Paragraph [0034].
Therefore, it would have been obvious to made to a person having ordinary skill in the art at the time the claimed invention made to provide U.S. Patent No. 12,125,737 with a hafnium oxide gate dielectric as taught by Brask et al. because HfO2 gate dielectric layer provides excellent thermal stability and high dielectric constant which effectively gate current leakage can be reduced.
Claims 8-10 and 12-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims of U.S. Patent No.12,243,765. Although the claims at issue are not identical, they are not patentably distinct from each other because of the followings:
Although the conflicting claims are not identical, the scope of the claimed limitations of the instant application as claimed in claims 8-10 and 12-20 is similar to that of the claimed limitations of U.S. Patent No. 12,243,765 as claimed in claims 7-20. Therefore, the claims are not patentably distinct from each other.
The instant application:
8. A method of fabricating a 3D semiconductor device, the method comprising: forming a first level comprising a first single crystal layer, wherein said first level comprises first transistors, and wherein each of said first transistors comprises a single crystal channel; forming a first metal layer in said first level; forming a second metal layer overlaying said first metal layer; forming memory control circuits in said first level; forming a second level comprising a plurality of second transistors, wherein at least one of said plurality of second transistors comprises a metal gate; forming a third level comprising a plurality of third transistors; forming a fourth level comprising a plurality of fourth transistors, wherein said second level comprises a plurality of first memory cells, wherein said fourth level comprises a plurality of second memory cells; bonding said second level to said first level, wherein said memory control circuits comprise control of data written into said plurality of first memory cells and into said plurality of second memory cells; and further comprising: forming a plurality of Through Silicon Vias ("TSVs") in said first level.
9. The method according to claim 8, further comprising: forming metal pads and metal pins for connecting said second level to said first level.
10. The method according to claim 8, further comprising: fabricating at least one Phase-Lock-Loop ("PLL") circuit or at least one Digital-Lock-Loop ("DLL") circuit.
11. The method according to claim 8, wherein at least one of said transistors comprises a hafnium oxide gate dielectric.
12. The method according to claim 8, wherein said memory cells are DRAM type memory cells.
13. The method according to claim 8, further comprising: configuring at least one of said first transistors to control power delivery for at least one of said plurality of third transistors.
14. The method according to claim 8, further comprising: forming pads for connecting inputs and outputs of said device to an external device, wherein said pads are disposed underneath said first single crystal layer.
15. A method of fabricating a 3D semiconductor device, the method comprising: forming a first level comprising a first single crystal layer, wherein said first level comprises first transistors, and wherein each of said first transistors comprises a single crystal channel; forming a first metal layer in said first level; forming a second metal layer overlaying said first metal layer; forming memory control circuits in said first level; forming a second level comprising a plurality of second transistors, wherein at least one of said plurality of second transistors comprises a metal gate; forming a third level comprising a plurality of third transistors; forming a fourth level comprising a plurality of fourth transistors, wherein said second level comprises a plurality of first memory cells, wherein said fourth level comprises a plurality of second memory cells, wherein said memory control circuits comprise control of data written into said first memory cells and into said second memory cells, and wherein said first level comprises at least one Phase-Lock-Loop ("PLL") circuit or at least one Digital-Lock-Loop ("DLL") circuit.
16. The method according to claim 15, further comprising: forming metal pads and metal pins for connecting said second level to said first level.
17. The method according to claim 15, further comprising: forming a plurality of Through Silicon Vias ("TSVs") in said first level
18. The method according to claim 15, wherein said memory cells are DRAM type memory cells.
19. The method according to claim 15, further comprising: configuring at least one of said first transistors to control power delivery for at least one of said plurality of third transistors.
20. The method according to claim 15, further comprising: forming pads for connecting inputs and outputs of said device to an external device, wherein said pads are disposed underneath said first single crystal layer.
U.S. Patent No. 12,243,765:
8. A 3D semiconductor device, the device comprising: a first level comprising a first single crystal layer, said first level comprising first transistors, wherein each of said first transistors comprises a single crystal channel; a first metal layer; a second metal layer overlaying said first metal layer; a second level comprising a plurality of second transistors, said second level overlaying said first level; a third level comprising a plurality of third transistors, said third level overlaying said second level; a fourth level comprising a plurality of fourth transistors, said fourth level overlaying said third level, wherein said second level comprises a plurality of first memory cells, wherein each of said plurality of first memory cells comprises at least one of said second transistors, wherein said fourth level comprises a plurality of second memory cells, wherein each of said plurality of second memory cells comprises at least one of said fourth transistors, wherein said first level comprises memory control circuits, wherein at least one of said second transistors comprises a metal gate, wherein said memory control circuits control writing to said plurality of second memory cells, and wherein said third level comprises at least four independently controlled memory arrays.
9. The device according to claim 8, further comprising: metal pads and metal pins for connecting said second level to said first level.
10. The device according to claim 8, further comprising: at least one Phase-Lock-Loop ("PLL") circuit or at least one Digital-Lock-Loop ("DLL") circuit.
11. The device according to claim 8, wherein said first level comprises a plurality of Through Silicon Via ("TSV").
12. The device according to claim 8, wherein said memory cells are DRAM type memory cells.
13. The device according to claim 8, wherein at least one of said first transistors controls power delivery for at least one of said third transistors.
14. The device according to claim 8, further comprising: pads for connecting inputs and outputs of said device to an external device, wherein said pads are disposed underneath said first single crystal layer.
15. A 3D semiconductor device, the device comprising: a first level comprising a first single crystal layer, said first level comprising first transistors, wherein each of said first transistors comprises a single crystal channel; a first metal layer; a second metal layer overlaying said first metal layer; a second level comprising a plurality of second transistors, said second level overlaying said first level; a third level comprising a plurality of third transistors, said third level overlaying said second level; and a fourth level comprising a plurality of fourth transistors, said fourth level overlaying said third level, wherein said second level comprises a plurality of first memory cells, wherein each of said plurality of first memory cells comprises at least one of said second transistors, wherein said fourth level comprises a plurality of second memory cells, wherein each of said plurality of second memory cells comprises at least one of said fourth transistors, wherein said first level comprises memory control circuits, wherein at least one of said second transistors comprises a metal gate, wherein said memory control circuits control writing to said plurality of second memory cells, and wherein said first level is bonded to said second level.
17. The device according to claim 15, further comprising: at least one Phase-Lock-Loop ("PLL") circuit or at least one Digital-Lock-Loop ("DLL") circuit.
16. The device according to claim 15, further comprising: metal pads and metal pins for connecting said second level to said first level.
20. The device according to claim 15, wherein said first level comprises a plurality of Through Silicon Via ("TSV").
18. The device according to claim 15, wherein said memory cells are DRAM type memory cells.
19. The device according to claim 15, wherein at least one of said first transistors controls power delivery for at least one of said third transistors.
7. The device according to claim 1, further comprising: pads for connecting inputs and outputs of said device to an external device, wherein said pads are disposed underneath said first single crystal layer.
Claims 1-7 and 11 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1-7 of U.S. Patent No. 12,243,765 in view of Brask et al. (US 2007/0001173).
The instant application:
1. A method of fabricating a 3D semiconductor device, the method comprising: forming a first level comprising a first single crystal layer, wherein said first level comprises first transistors, and wherein each of said first transistors comprises a single crystal channel; forming a first metal layer in said first level; forming a second metal layer overlaying said first metal layer; forming memory control circuits in said first level; forming a second level comprising a plurality of second transistors, wherein at least one of said plurality of second transistors comprises a metal gate; forming a third level comprising a plurality of third transistors; and forming a fourth level comprising a plurality of fourth transistors, wherein said second level comprises a plurality of first memory cells, wherein said fourth level comprises a plurality of second memory cells, wherein said memory control circuits comprise control of data written into said first memory cells and into said second memory cells, and wherein at least one of said transistors comprises a hafnium oxide gate dielectric.
3. The method according to claim 1, further comprising: fabricating at least one Phase-Lock-Loop ("PLL") circuit or at least one Digital-Lock-Loop ("DLL") circuit.
2. The method according to claim 1, further comprising: forming metal pads and metal pins for connecting said second level to said first level.
4. The method according to claim 1, further comprising: forming a plurality of Through Silicon Vias ("TSVs") in said first level.
5. The method according to claim 1, wherein said memory cells are DRAM type memory cells.
6. The method according to claim 1, further comprising: configuring at least one of said first transistors to control power delivery for at least one of said plurality of third transistors.
7. The method according to claim 1, further comprising: forming pads for connecting inputs and outputs of said device to an external device, wherein said pads are disposed underneath said first single crystal layer.
11. The method according to claim 8, wherein at least one of said transistors comprises a hafnium oxide gate dielectric.
U.S. Patent No. 12,243,765:
1. A 3D semiconductor device, the device comprising: a first level comprising a first single crystal layer, said first level comprising first transistors, wherein each of said first transistors comprises a single crystal channel; a first metal layer; a second metal layer overlaying said first metal layer; a second level comprising a plurality of second transistors, said second level overlaying said first level; a third level comprising a plurality of third transistors, said third level overlaying said second level; a fourth level comprising a plurality of fourth transistors, said fourth level overlaying said third level, wherein said second level comprises a plurality of first memory cells, wherein each of said plurality of first memory cells comprises at least one of said second transistors, wherein said fourth level comprises a plurality of second memory cells, wherein each of said plurality of second memory cells comprises at least one of said fourth transistors, wherein said first level comprises memory control circuits, and wherein said memory control circuits control writing to said plurality of second memory cells; and at least one Phase-Lock-Loop ("PLL") circuit or at least one Digital-Lock-Loop ("DLL") circuit.
2. The device according to claim 1, further comprising: metal pads and metal pins for connecting said second level to said first level.
4. The device according to claim 1, wherein said first level comprises a plurality of Through Silicon Via ("TSV").
5. The device according to claim 1, wherein said memory cells are DRAM type memory cells.
6. The device according to claim 1, wherein at least one of said first transistors controls power delivery for at least one of said third transistors.
7. The device according to claim 1, further comprising: pads for connecting inputs and outputs of said device to an external device, wherein said pads are disposed underneath said first single crystal layer.
Although it is well-known in the art use of HfO2 (hafnium oxide) gate dielectric layer for its excellent thermal stability and high dielectric constant which effectively reduces gate leakage current, U.S. Patent No. 12,243,765 does not claim that wherein at least one of said transistors comprises a hafnium oxide gate dielectric.
Brask et al. disclose semiconductor device comprises high dielectric constant hafnium oxide gate dielectric (250). See Paragraph [0034].
Therefore, it would have been obvious to made to a person having ordinary skill in the art at the time the claimed invention made to provide U.S. Patent No. 12,243,765 with a hafnium oxide gate dielectric as taught by Brask et al. because HfO2 gate dielectric layer provides excellent thermal stability and high dielectric constant which effectively gate current leakage can be reduced.
Claims 1-20 provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of copending Application No.19/234,514 (reference application). Although the claims at issue are not identical, they are not patentably distinct from each other because of the followings:
Although the conflicting claims are not identical, the scope of the claimed limitations of the instant application as claimed in claims 1-20 is similar to that of the claimed limitations of copending Application No.19/234,514 as claimed in claims 1-20. Therefore, the claims are not patentably distinct from each other.
The instant application:
1. A method of fabricating a 3D semiconductor device, the method comprising: forming a first level comprising a first single crystal layer, wherein said first level comprises first transistors, and wherein each of said first transistors comprises a single crystal channel; forming a first metal layer in said first level; forming a second metal layer overlaying said first metal layer; forming memory control circuits in said first level; forming a second level comprising a plurality of second transistors, wherein at least one of said plurality of second transistors comprises a metal gate; forming a third level comprising a plurality of third transistors; and forming a fourth level comprising a plurality of fourth transistors, wherein said second level comprises a plurality of first memory cells, wherein said fourth level comprises a plurality of second memory cells, wherein said memory control circuits comprise control of data written into said first memory cells and into said second memory cells, and wherein at least one of said transistors comprises a hafnium oxide gate dielectric.
2. The method according to claim 1, further comprising: forming metal pads and metal pins for connecting said second level to said first level.
3. The method according to claim 1, further comprising: fabricating at least one Phase-Lock-Loop ("PLL") circuit or at least one Digital-Lock-Loop ("DLL") circuit.
4. The method according to claim 1, further comprising: forming a plurality of Through Silicon Vias ("TSVs") in said first level.
5. The method according to claim 1, wherein said memory cells are DRAM type memory cells.
6. The method according to claim 1, further comprising: configuring at least one of said first transistors to control power delivery for at least one of said plurality of third transistors.
7. The method according to claim 1, further comprising: forming pads for connecting inputs and outputs of said device to an external device, wherein said pads are disposed underneath said first single crystal layer.
8. A method of fabricating a 3D semiconductor device, the method comprising: forming a first level comprising a first single crystal layer, wherein said first level comprises first transistors, and wherein each of said first transistors comprises a single crystal channel; forming a first metal layer in said first level; forming a second metal layer overlaying said first metal layer; forming memory control circuits in said first level; forming a second level comprising a plurality of second transistors, wherein at least one of said plurality of second transistors comprises a metal gate; forming a third level comprising a plurality of third transistors; forming a fourth level comprising a plurality of fourth transistors, wherein said second level comprises a plurality of first memory cells, wherein said fourth level comprises a plurality of second memory cells; bonding said second level to said first level, wherein said memory control circuits comprise control of data written into said plurality of first memory cells and into said plurality of second memory cells; and further comprising: forming a plurality of Through Silicon Vias ("TSVs") in said first level.
9. The method according to claim 8, further comprising: forming metal pads and metal pins for connecting said second level to said first level.
10. The method according to claim 8, further comprising: fabricating at least one Phase-Lock-Loop ("PLL") circuit or at least one Digital-Lock-Loop ("DLL") circuit.
11. The method according to claim 8, wherein at least one of said transistors comprises a hafnium oxide gate dielectric.
12. The method according to claim 8, wherein said memory cells are DRAM type memory cells.
13. The method according to claim 8, further comprising: configuring at least one of said first transistors to control power delivery for at least one of said plurality of third transistors.
14. The method according to claim 8, further comprising: forming pads for connecting inputs and outputs of said device to an external device, wherein said pads are disposed underneath said first single crystal layer.
15. A method of fabricating a 3D semiconductor device, the method comprising: forming a first level comprising a first single crystal layer, wherein said first level comprises first transistors, and wherein each of said first transistors comprises a single crystal channel; forming a first metal layer in said first level; forming a second metal layer overlaying said first metal layer; forming memory control circuits in said first level; forming a second level comprising a plurality of second transistors, wherein at least one of said plurality of second transistors comprises a metal gate; forming a third level comprising a plurality of third transistors; forming a fourth level comprising a plurality of fourth transistors, wherein said second level comprises a plurality of first memory cells, wherein said fourth level comprises a plurality of second memory cells, wherein said memory control circuits comprise control of data written into said first memory cells and into said second memory cells, and wherein said first level comprises at least one Phase-Lock-Loop ("PLL") circuit or at least one Digital-Lock-Loop ("DLL") circuit.
17. The method according to claim 15, further comprising: forming a plurality of Through Silicon Vias ("TSVs") in said first level
16. The method according to claim 15, further comprising: forming metal pads and metal pins for connecting said second level to said first level.
18. The method according to claim 15, wherein said memory cells are DRAM type memory cells.
19. The method according to claim 15, further comprising: configuring at least one of said first transistors to control power delivery for at least one of said plurality of third transistors.
20. The method according to claim 15, further comprising: forming pads for connecting inputs and outputs of said device to an external device, wherein said pads are disposed underneath said first single crystal layer.
Co-pending Application No. 19/234,514:
1. A 3D semiconductor device, the device comprising: a first level comprising a first single crystal layer, said first level comprising first transistors, wherein each of said first transistors comprises a single crystal channel; a first metal layer, a second metal layer connected to said first metal layer; at least one Phase-Lock-Loop (“PLL”) circuit or at least one Digital-Lock-Loop (“DLL”) circuit; a second level comprising a plurality of second transistors, said second level overlaying said first level; a third level comprising a plurality of third transistors, said third level overlaying said second level; a fourth level comprising a plurality of fourth transistors, said fourth level overlaying said third level, wherein said second level comprises a plurality of first memory cells, wherein each of said plurality of first memory cells comprises at least one of said second transistors, wherein said fourth level comprises a plurality of second memory cells, wherein each of said plurality of second memory cells comprises at least one of said fourth transistors, wherein said first level comprises memory control circuits, wherein at least one of said second transistors comprises a metal gate, wherein said memory control circuits control writing to said plurality of second memory cells, and wherein at least one of said second transistors comprises a hafnium oxide gate dielectric.
2. The device according to claim 1, further comprising: metal pads and metal pins for connecting said second level to said first level.
10. The device according to claim 8, further comprising: at least one Phase-Lock-Loop (“PLL”) circuit or at least one Digital-Lock-Loop (“DLL”) circuit.
4. The device according to claim 1, wherein said first level comprises a plurality of Through Silicon Via (“TSV”).
5. The device according to claim 1, wherein said memory cells are DRAM type memory cells.
6. The device according to claim 1, wherein at least one of said first transistors controls power delivery for at least one of said third transistors.
7. The device according to claim 1, further comprising: pads for connecting inputs and outputs of said device to an external device, wherein said pads are disposed underneath said first single crystal layer.
8. A 3D semiconductor device, the device comprising: a first level comprising a first single crystal layer, said first level comprising first transistors, wherein each of said first transistors comprises a single crystal channel; a first metal layer, a second metal layer connected to said first metal layer; pads for connecting inputs and outputs of said device to an external device, wherein said pads are disposed underneath said first single crystal layer; a second level comprising a plurality of second transistors, said second level overlaying said first level; a third level comprising a plurality of third transistors, said third level overlaying said second level; a fourth level comprising a plurality of fourth transistors, said fourth level overlaying said third level, wherein said second level comprises a plurality of first memory cells, wherein each of said plurality of first memory cells comprises at least one of said second transistors, wherein said fourth level comprises a plurality of second memory cells, wherein each of said plurality of second memory cells comprises at least one of said fourth transistors, wherein said first level comprises memory control circuits, wherein at least one of said second transistors comprises a metal gate, wherein said memory control circuits control writing to said plurality of second memory cells, and wherein said first level comprises a plurality of Through Silicon Via (“TSV”).
9. The device according to claim 8, further comprising: metal pads and metal pins for connecting said second level to said first level.
10. The device according to claim 8, further comprising: at least one Phase-Lock-Loop (“PLL”) circuit or at least one Digital-Lock-Loop (“DLL”) circuit.
Claim,1. wherein at least one of said second transistors comprises a hafnium oxide gate dielectric.
12. The device according to claim 8, wherein said memory cells are DRAM type memory cells.
13. The device according to claim 8, wherein at least one of said first transistors controls power delivery for at least one of said third transistors.
7. The device according to claim 1, further comprising: pads for connecting inputs and outputs of said device to an external device, wherein said pads are disposed underneath said first single crystal layer.
15. A 3D semiconductor device, the device comprising: a first level comprising a first single crystal layer, said first level comprising first transistors, wherein each of said first transistors comprises a single crystal channel; a first metal layer, a second metal layer overlaying said first metal layer; wherein said first level comprises a plurality of Through Silicon Via (“TSV”); a second level comprising a plurality of second transistors, said second level overlaying said first level; a third level comprising a plurality of third transistors, said third level overlaying said second level; and a fourth level comprising a plurality of fourth transistors, said fourth level overlaying said third level, wherein said second level comprises a plurality of first memory cells, wherein each of said plurality of first memory cells comprises at least one of said second transistors, wherein said fourth level comprises a plurality of second memory cells, wherein each of said plurality of second memory cells comprises at least one of said fourth transistors, wherein said first level comprises memory control circuits, wherein at least one of said second transistors comprises a metal gate, wherein said memory control circuits control reading from said plurality of second memory cells, wherein said memory control circuits control writing to said plurality of third memory cells, and wherein said first level is bonded to said second level.
17. The device according to claim 15, further comprising: at least one Phase-Lock-Loop (“PLL”) circuit or at least one Digital-Lock-Loop (“DLL”) circuit.
16. The device according to claim 15, further comprising: metal pads and metal pins for connecting said second level to said first level.
18. The device according to claim 15, wherein said memory cells are DRAM type memory cells.
19. The device according to claim 15, wherein at least one of said first transistors controls power delivery for at least one of said third transistors.
7. The device according to claim 1, further comprising: pads for connecting inputs and outputs of said device to an external device, wherein said pads are disposed underneath said first single crystal layer.
This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure Atwood et al. (US 2003/0227041), Yu et al. (US 2008/0124845) and Lee (US 2009/0325343) also disclose 3D semiconductor device.
Correspondence
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BROOK KEBEDE whose telephone number is 571-272-1862. The examiner can normally be reached Monday Friday 8:00 AM 5:00 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jeff Natalini can be reached at 571-272-2266. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/BROOK KEBEDE/
Primary Examiner, Art Unit 2894
/BK/
February 15, 2026