DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-4, 9- 18 and 20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Yang et al., US 2023/0306906 A1 (hereinafter “Yang”).
The applied reference has a common assignee with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2). This rejection under 35 U.S.C. 102(a)(2) might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C. 102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B) if the same invention is not being claimed; or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed in the reference and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement.
Regarding claim 1, Yang discloses a pixel circuit (FIGS. 1-3, pixel PXL at [0058]-[0061]) comprising:
a first transistor (FIGS. 3 and 21, and T1) including a control electrode connected to a first node (FIGS. 3 and 21, T1 control electrode connected to N1), a first electrode connected to a second node (FIGS. 3 and 21, first electrode of T1 connected to N2) and a second electrode connected to a third node (FIG. 3 and 21, second electrode of T1 connected to N3);
a second transistor (FIG. 3 and 21, T2 at [0084]), which applies a data voltage to the first node in response to a write gate signal (T2 connected to DLj and GW accordingly applying data voltage to N1);
a third transistor (FIGS. 3 and 21 (M5) and T8 and [0090]), which applies a first power voltage (FIG. 3 and 21, VDD) to the second node (N2) in response to an emission signal (EM1);
a fourth transistor (FIG. 3 and 21, and T6, with EM2 signal at [0088]), which connects the third node (N3) and a fourth node (N5) in response to a reset signal (EM2 signal at [0088]);
a fifth transistor (FIG. 3 and 21, and T7 and [0089]), which applies an initialization voltage (VAINIT) to the fourth node (N5) in response to a bias signal (FIG. 3 and 21, EB and at [0089]) ; and
a light emitting element (FIG. 3 and 21 and LD at [0089])including a first electrode connected to the fourth node (LD electrode connected to N5) and a second electrode (Bottom electrode of LD), which receives a second power voltage (bottom electrode receives VSS at [0078]),
wherein the emission signal toggles between a first voltage level and a second voltage level (FIGS. 5 and 22 and EM1 toggles between low and high),
wherein the first voltage level is higher than the second voltage level (FIG. 5 and EM1 toggles between low and high one being higher than the other),
wherein the reset signal toggles between a third voltage level and a fourth voltage level (FIGS. 5 and 22 and EM2 toggles between low and high one being higher than the other),
wherein the third voltage level is higher than the fourth voltage level (FIGS. 5 and 22 and EM2 toggles between low and high one being higher than the other), and
wherein the third voltage level is lower than the first voltage level (FIGS. 5 and 22 with EM2 having a voltage level lower than EM1 and FIG. 22 with EM2 dropping lower at TP3 whereas EM1 would still be high in that scenario [0156]-[0157] and [0188]-[0191]).
Regarding claim 2, Yang discloses the pixel circuit of claim 1 (see above), wherein the third voltage level is a voltage such that the fourth transistor is weakly turned on so that the fourth transistor operates in a linear region (FIGS. 3-5 and 21-22 and T6 and M6 and [0088] and [0187]-[0191]).
Regarding claim 3, Yang discloses the pixel circuit of claim 1 (see above), wherein in an emission period in which the light emitting element emits, the fourth transistor is weakly turned on (FIGS. 3-5 and 21-22 T6 and M6 and [0088] and [0187]-[0191]).
Regarding claim 4, Yang discloses the pixel circuit of claim 3 (see above), wherein in the emission period, the fourth transistor operates in a linear region (FIGS. 3-5 and 21-22 T6 and M6 and [0088] and [0187]-[0191]).
Regarding claim 9, Yang discloses the pixel circuit of claim 1 (see above), wherein a frame period in which the pixel circuit is driven includes a first to sixth periods (FIG. 5 TP1-TP3), and wherein in the first period (FIG. 5 TP1-TP2), the emission signal has the second voltage level (EM1 is low), the bias signal has an activation level (FIG. 5 EB is high), and the reset signal has the fourth voltage level (FIG. 5 and EM2 is high and [0096]-[0108]).
Regarding claim 18, it is similar in scope to claim 1 above, the only difference being claim 18 is directed to a display device (FIG. 1, and display device 100) comprising: a display panel (FIG. 1, and display panel 110) including a pixel circuit (FIGS. 1-3, pixel PXL); a gate driver (FIG. 1, and gate drivers 121, 122, 123), which outputs a gate signal including a write gate signal to the pixel circuit (FIG. 1, and gate signals and write signals GCL1, GIL1, GWL… GCLn, GILn, GWLn); an emission driver (FIG. 1, and emission drivers 151, 152, 153), which outputs an emission signal to the pixel circuit (FIG. 1, and emission signals EML11, EML21, EBL1… EML1n, EML2n, EBLn); a data driver (FIG. 1 data driver 130), which applies a data voltage to the pixel circuit (FIG. 1, DL1… DLm); and a driving controller (FIG. 1, and timing controller 140), which controls the gate driver (FIG. 1 and SCS1,SCS2, SCS3), the emission driver (FIG. 1 and ECS1,ECS2, ECS3) and the data driver (FIG. 1 and DCS), wherein the pixel circuit includes that of claim 1(see above). Therefore, claim 18 is similarly analyzed and rejected as claim 1.
Regarding claim 19, Yang discloses the display device of claim 18 (see above), wherein the third voltage level is a voltage such that the fourth transistor is weakly turned on (FIGS. 3-5 and 21-22 T6 and M6 and [0088] and [0187]-[0191]).
Regarding claim 20, it is similar in scope to claim 1 above, the only difference being claim 20 is directed to an electronic device (FIG. 1, and display device 100) comprising: a display panel (FIG. 1, and display panel 110) including a pixel circuit (FIGS. 1-3, pixel PXL); a gate driver (FIG. 1, and gate drivers 121, 122, 123), which outputs a gate signal including a write gate signal to the pixel circuit (FIG. 1, and gate signals and write signals GCL1, GIL1, GWL… GCLn, GILn, GWLn); an emission driver (FIG. 1, and emission drivers 151, 152, 153), which outputs an emission signal to the pixel circuit (FIG. 1, and emission signals EML11, EML21, EBL1… EML1n, EML2n, EBLn); a data driver (FIG. 1 data driver 130), which applies a data voltage to the pixel circuit (FIG. 1, DL1… DLm); and a driving controller (FIG. 1, and timing controller 140), which controls the gate driver (FIG. 1 and SCS1,SCS2, SCS3), the emission driver (FIG. 1 and ECS1,ECS2, ECS3) and the data driver (FIG. 1 and DCS), and a processor, which outputs the input control signal (FIG. 1 and [0069]), wherein the pixel circuit includes that of claim 1(see above).Therefore, claim 20 is similarly analyzed and rejected as claim 1.
Allowable Subject Matter
Claims 5-8 and 10-17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The cited prior art of record does not disclose the following combination of limitations of claim 5: wherein a frame period in which the pixel circuit is driven includes an initialization period, a write period following the initialization period, and an emission period following the write period, and wherein in the initialization period, the reset signal has the fourth voltage level, the emission signal has the second voltage level and the bias signal has an activation level.
By virtue of their dependency, claims 6-8 are also objected to.
The cited prior art of record does not disclose the following combination of limitations of claim 10: wherein in the second period, which follows the first period, the emission signal is changed from the second voltage level to the first voltage level, the bias signal has the activation level, and the reset signal has the third voltage level.
By virtue of their dependency, claims 11-14 are also objected to.
The cited prior art of record does not disclose the following combination of limitations of claim 15: wherein the second transistor includes a control electrode, which receives the write gate signal, a first electrode, which receives the data voltage and a second electrode connected to the first node, wherein the third transistor includes a control electrode, which receives the emission signal, a first electrode, which receives the first power voltage and a second electrode connected to the second node, wherein the fourth transistor includes a control electrode, which receives the emission signal, a first electrode connected to the third node and a second electrode connected to the fourth node, and wherein the fifth transistor includes a control electrode, which receives the bias signal, a first electrode, which receives the initialization voltage and a second electrode connected to the fourth node.
By virtue of their dependency, claims 16-17 are also objected to.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Lee et al., US 2024/0274079 A1: Abstract and FIGS. 2-5 illustrating pixel structure and driving method;
Gao et al., US 2022/0262310 A1: Abstract and FIGS. 1A-4 illustrating pixel circuit structure and reset signal application;
Wang et al., US 2022/0343852 A1: Abstract and FIGS. 7-10 and 13 and illustrating pixel circuit structure with reset signal delayed;
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SARVESH J. NADKARNI whose telephone number is (571)270-7562. The examiner can normally be reached 8AM-5PM M-F.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Benjamin C. Lee can be reached at (571)272-2963. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SARVESH J NADKARNI/Examiner, Art Unit 2629
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