DETAILED ACTION
Terminal Disclaimer
The response filed 6/25/26 states a terminal disclaimer was filed along with the claim amendment. But a terminal disclaimer was not received by the Patent Office. A terminal disclaimer is requested in the next response.
Response to Arguments
Applicant's arguments filed 6/25/26 have been fully considered but they are not persuasive.
It is argued that Chung fails to teach the claimed interposer body. The specification recites the interposer is a HTC, LCTE interposer having a core with though-vias and RDL’s on both sides. Chung teaches a routing structure that lacks a core and is a stack of dielectric layers with conductive layers, which is different from the claims.
Note that the claim does not require a core or a HTC, LCTE interposer. The claim only recites the interposer has an interposer body with at least a RDL. In Chung, the interposer body is the stack of dielectric layers and the conductive layers are the RDL.
Another argument is that the background section of Chung teaches away from using interposers.
Note that Chung (column 1, lines 43-53) does not teach away from interposers, it teaches away from using single through-silicon interposers. But other forms of interposers can be used, see Meyer et al, US 9,059,304, which teaches an interposer made of a stack of dielectric layers and conductive layers with RDL’s on each side. This is the same type of interposer as Chung’s interposer. This teaches that an interposer does not require a core with through-vias and an RDL.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1, and 18-20 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of copending Application No. 18/963300 (hereafter referred to as the reference). Although the claims at issue are not identical, they are not patentably distinct from each other because the only differences is the reference defines the first and second die of the present application as high-power die and lower-power die.
This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented.
Regarding claim 1, the reference claims a three dimensional (3D) integrated circuit (IC) package, comprising:
a substrate structure having a first surface and a second surface opposite to the first surface (claim 1, lines 3-4);
a first interposer disposed over the first surface of the substrate structure (claim 1, lines 7-8);
a second interposer disposed over the first interposer (claim 1, lines 9-10); and
a first semiconductor die (claim 1, lines 5) and a second semiconductor die (claim 1, lines 6) disposed over the first surface of the substrate structure, and the first semiconductor die and the second semiconductor die bonded to two opposite sides of the second interposer (claim 1, lines 7-10), respectively;
wherein the substrate structure comprises a thermal enhancement portion, and at least one of a thermal conductivity or a geometry of the thermal enhancement portion is different from that of other portions of the substrate structure (claim 1, lines 11-15).
The reference may not explicitly teach the interposers comprise an interposer body with at least a RDL at a side of the interposer body, but this is the definition of an interposer. An interposer inherently has an interposer body and a RDL.
With respect to claim 18, though the reference, which only claims it is a high thermal conductivity material (claim 4), fails to claim the thermal enhancement portion comprises a material having a thermal conductivity substantially greater than about a thermal conductivity of silicon, it would have been obvious to one ordinary skill in the art at the time of the invention to optimize the thermal conductivity through routine experimentation (MPEP 2144.05).
As to claim 19, the reference (claim 4) claims a top surface and a bottom surface of the material are coplanar with the first surface and the second surface of the substrate structure.
In re claim 20, though the reference fails to teach the thermal enhancement portion further comprises a plurality of through vias penetrating completely the material, it would have been obvious to one of ordinary skill in the art at the time of the invention to use a plurality of through vias (the opening of claim 4) in the invention of the reference because the mere duplication of parts has no patentable significance unless a new and unexpected result is produced (In re Harza, 124 USPQ 378 (CCPA 1960)).
Claim 9-12 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of U.S. Patent No. 18/963300 (hereafter referred to as the reference), in view of Subrahmanyam et al., US 2021/0351106.
With respect to claim 9, the reference fails to teach a liquid immersion cooling structure disposed over the first semiconductor die or the second semiconductor die, wherein the liquid immersion cooling structure comprises a built-in channel configured for passing a coolant through the liquid immersion cooling structure.
Subrahmanyam (figure 6A) teaches a liquid immersion cooling structure 944 disposed over the first semiconductor die 942 or the second semiconductor die, wherein the liquid immersion cooling structure comprises a built-in channel 948 configured for passing a coolant 946 through the liquid immersion cooling structure 944.
It would have been obvious to one of ordinary skill in the art at the time of the invention to use the structure of Subrahmanyam in the invention of the reference because it is conventionally known and used in the art cooling method. The use of conventional materials to perform their known functions is obvious (MPEP 2144.07).
As to claim 10, though Subrahmanyam (figure 6A), which teaches millimeter (paragraph 0040) nozzles 945, fails to teach the liquid immersion cooling structure further comprises one or more micro-nozzles facing the first semiconductor die or the second semiconductor die, it would have been obvious to one ordinary skill in the art at the time of the invention to optimize the nozzle size through routine experimentation (MPEP 2144.05).
In re claim 11, Subrahmanyam (figure 6A) teaches the coolant 646 passing from an upper side of the first semiconductor die or the second semiconductor die toward a lateral side of the first semiconductor die or the second semiconductor die.
Concerning claim 12, Subrahmanyam (figure 6A) teaches the liquid immersion cooling structure further comprises a supporting portion 639 disposed on the substrate structure, and the supporting portion comprises an opening (VAPOR).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, and 18-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chung et al., US 6,717,812, in view of Lee et al., US 7,714,451.
Pertaining to claim 1, Chung (figure 3) teaches a three dimensional (3D) integrated circuit (IC) package, comprising:
a substrate structure 30 having a first surface and a second surface opposite to the first surface;
a first interposer 2b disposed over the first surface of the substrate structure 30;
a second interposer 20 disposed over the first interposer 2b; and
a first semiconductor die 2a and a second semiconductor die 26 disposed over the first surface of the substrate structure 30, and the first semiconductor die 2a and the second semiconductor die 26 bonded (through 21a above 2a & unlabeled bumps under 26)) to two opposite sides of the second interposer 20, respectively; and
wherein each of the first interposer 2b (column 2, lines 34-40) and the second interposer 20 (column 5, lines 40-49) comprises an interposer body with at least a redistribution layer (RDL) at a side of the interposer body.
Chung fails to teach the substrate structure 30 comprises a thermal enhancement portion, and at least one of a thermal conductivity or a geometry of the thermal enhancement portion is different from that of other portions of the substrate structure.
Lee (figure 5) teaches the substrate structure 102 comprises a thermal enhancement portion 104, and at least one of a thermal conductivity or a geometry of the thermal enhancement portion is different from that of other portions of the substrate structure (insulating substate and 104 is metal).
It would have been obvious to one of ordinary skill in the art at the time of the invention to use the thermal enhancement portion 104 of Lee in the invention of Chung because Lee teaches it provides “unavailable solutions, capabilities, and functional advantages for dissipating heat. The resulting process and configurations are straightforward, economical, uncomplicated, highly versatile and effective, use conventional technologies, and are thus readily suited for manufacturing semiconductor devices that are fully compatible with conventional manufacturing processes and technologies.” (column 7, lines 1-7).
In claim 18, Lee (column 4, lines 1-4 teaches copper) teaches the thermal enhancement portion 104 comprises a material having a thermal conductivity substantially greater than about a thermal conductivity of silicon. Copper has a higher thermal conductivity than silicon.
Regarding claim 19, though Lee (figure 5) fails to teach a top surface and a bottom surface of the material are coplanar with the first surface and the second surface of the substrate structure, it would have been obvious to one of ordinary skill in the art at the time of the invention to use a coplanar configuration in the invention of Lee because it is a conventionally known and used equivalent configuration. The substitution of one known equivalent technique for another may be obvious even if the prior art does not expressly suggest the substitution (Ex parte Novak 16 USPQ 2d 2041 (BPAI 1989); In re Mostovych 144 USPQ 38 (CCPA 1964); In re Leshin 125 USPQ 416 (CCPA 1960); Graver Tank & Manufacturing Co. V. Linde Air Products Co. 85 USPQ 328 (USSC 1950).
With respect to claim 20, Lee (figure 5) teaches the thermal enhancement portion 104 further comprises a plurality of through vias 104 penetrating completely the material.
Claim(s) 9-12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chung et al., US 6,717,812, in view of Lee et al., US 7,714,451, as applied to claim 1 above, and further in view of Subrahmanyam et al., US 2021/0351106.
With respect to claim 9, Chung fails to teach a liquid immersion cooling structure disposed over the first semiconductor die or the second semiconductor die, wherein the liquid immersion cooling structure comprises a built-in channel configured for passing a coolant through the liquid immersion cooling structure.
Subrahmanyam (figure 6A) teaches a liquid immersion cooling structure 944 disposed over the first semiconductor die 942 or the second semiconductor die, wherein the liquid immersion cooling structure comprises a built-in channel 948 configured for passing a coolant 946 through the liquid immersion cooling structure 944.
It would have been obvious to one of ordinary skill in the art at the time of the invention to use the structure of Subrahmanyam in the invention of Chung because it is conventionally known and used in the art cooling method. The use of conventional materials to perform their known functions is obvious (MPEP 2144.07).
As to claim 10, though Subrahmanyam (figure 6A), which teaches millimeter (paragraph 0040) nozzles 945, fails to teach the liquid immersion cooling structure further comprises one or more micro-nozzles facing the first semiconductor die or the second semiconductor die, it would have been obvious to one ordinary skill in the art at the time of the invention to optimize the nozzle size through routine experimentation (MPEP 2144.05).
In re claim 11, Subrahmanyam (figure 6A) teaches the coolant 646 passing from an upper side of the first semiconductor die or the second semiconductor die toward a lateral side of the first semiconductor die or the second semiconductor die.
Concerning claim 12, Subrahmanyam (figure 6A) teaches the liquid immersion cooling structure further comprises a supporting portion 639 disposed on the substrate structure, and the supporting portion comprises an opening (VAPOR).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The cited prior art, Meyer et al, US 9,059,304, teach interposers are more than just a core with at least a RDL, as alleged in the response filed 6/25/26.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry should be directed to DAVID A ZARNEKE at (571)272-1937. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matt Landau can be reached at 571-272-1731. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DAVID A ZARNEKE/Primary Examiner, Art Unit 2891 7/11/26
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