Prosecution Insights
Last updated: October 25, 2026

Will Semiconductor (Shanghai) Co. Ltd.

Technology area: Semiconductors, Circuits & Optics

3 pending office actions • 3 art units • 3 examiners • 0 of 3 (0%) have an AI response strategy ready • 6 patents granted in the last 365 days

Analysis

Will Semiconductor (Shanghai) Co. Ltd. is currently managing 3 pending office actions within the Semiconductors, Circuits & Optics technology area. This level of activity indicates a focused effort to protect specialized electronic and optical innovations. The 3 pending actions suggest a deliberate and controlled approach to patent prosecution in these high-tech fields.

The prosecution is spread across 3 distinct examiners and 3 distinct art units. This 1:1 ratio between pending actions and examiners indicates that each matter is being handled independently by a different individual in a different administrative section. This structure prevents any single examiner from having a dominant influence over the company's current Semiconductors, Circuits & Optics portfolio.

PUENTES, DANIEL CALRISSIAN is identified as the busiest examiner, currently overseeing 1 busiest examiner pending office action. Because this examiner only manages 1 of the 3 total actions, the workload is evenly distributed. Practitioners must therefore prepare for 3 distinct examination styles across the 3 art units to successfully navigate the current prosecution cycle.

Written from this page's own data; every figure is computed from USPTO records and verified before publication.

Portfolio Summary

3
Total Pending OAs
3
Non-Final OAs
0
Final Rejections
0
Advisory / Quayle

Response Deadline Pressure

Based on the USPTO statutory response window for each pending office action. 2 of the docket's apps have a known mailing date; the rest are excluded from the tile counts.

2
Overdue
0
Due this week
0
Due this month
0
Due in next 60 days
0
Due later

Case Difficulty Mix

Difficulty is derived from the rejection statutes on the most recent pending office action. §101-driven and multi-statute cases are graded Hard; §112-only and obviousness-type double-patenting cases are graded Easy; everything else is Medium. "Unknown" means we have not yet parsed a statute for that office action.

1
Hard (33%)
0
Medium (0%)
2
Easy (67%)
0
Unknown (0%)

Rejection Statute Mix

BucketCases
§112 only2 (67%)
Multi-statute (no §101)1 (33%)

Industry Mix

How the docket's pending cases split across USPTO tech-center bands.

0
Life Sciences
0% of docket
0
Information Tech
0% of docket
0
Communications
0% of docket
3
Semiconductors
100% of docket
0
Mechanical / Eng
0% of docket
0
Business / Other
0% of docket

Time-on-OA Estimate

Manual office-action response work runs about 10 hours per case. The time-saved bands below show what IP Author's prosecution pipeline typically delivers — a conservative 20% on the low end, 35% in the middle, 50% on the high end.

30 h
Manual time on pending OAs
6 h
Time saved (low, 20%)
10 h
Time saved (mid, 35%)
0.3 wks
FTE-weeks freed (mid)

Top Examiners on this docket

ExaminerApps on this docketAllow rateInterview lift
PUENTES, DANIEL CALRISSIAN 1 88.7% +3.1%
ROLAND, CHRISTOPHER M 1 64.6% +20.9%
AHMADI, MOHSEN 1 86.9% +9.5%

Quick Wins (1)

Cases in front of an examiner with an allow rate of 80%+ where the difficulty is Easy or Medium. The top 1 ordered by deadline are shown.

App #TitleExaminerDue in
18886019 SEMICONDUCTOR INTEGRATED CIRCUIT PUENTES, DANIEL CALRISSIAN 37d overdue

Hard Cases (1)

Multi-statute / §101-driven matters, or cases in front of an examiner with an allow rate under 30%. The top 1 ordered by deadline are shown.

App #TitleExaminerDue in
18073356 SEMICONDUCTOR DEVICE AHMADI, MOHSEN 23d overdue

Interview Candidates (1)

Cases in front of an examiner whose interview lift is 10 percentage points or more — i.e. interviewed cases historically resolve more favorably than non-interviewed ones. The top 1 ordered by deadline are shown.

App #TitleExaminerDue in
18570253 METHOD FOR PREPARING SHIELDED GATE SEMICONDUCTOR DEVICE STRUCTURE, AND SHIELDED GATE SEMICONDUCTOR DEVICE STRUCTURE ROLAND, CHRISTOPHER M —

Top Art Units

Art UnitApps
2849 1
2893 1
2896 1

Pending Office Actions

App #TitleExaminerArt UnitStatutesStatusDue inAIFiled
18886019 SEMICONDUCTOR INTEGRATED CIRCUIT PUENTES, DANIEL CALRISSIAN 2849 §112 Non-Final OA 37d overdue Pending Sep 16, 2024
18570253 METHOD FOR PREPARING SHIELDED GATE SEMICONDUCTOR DEVICE STRUCTURE, AND SHIELDED GATE SEMICONDUCTOR DEVICE STRUCTURE ROLAND, CHRISTOPHER M 2893 §112 Non-Final OA — Pending Dec 14, 2023
18073356 SEMICONDUCTOR DEVICE AHMADI, MOHSEN 2896 §103§112 Non-Final OA 23d overdue Pending Dec 01, 2022

Managing Will Semiconductor (Shanghai) Co. Ltd.'s Patent Portfolio?

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Frequently Asked Questions

How many pending USPTO office actions does Will Semiconductor (Shanghai) Co. Ltd. have?

Will Semiconductor (Shanghai) Co. Ltd. has 3 pending office actions as of October 2026, spread across 3 art units and 3 examiners.

Which USPTO examiner handles the most Will Semiconductor (Shanghai) Co. Ltd. applications?

Daniel Calrissian Puentes has the most, with 1 of Will Semiconductor (Shanghai) Co. Ltd.'s pending office actions.

What technology area are Will Semiconductor (Shanghai) Co. Ltd.'s patent applications in?

Mostly Semiconductors, Circuits & Optics (USPTO Tech Center 2800), based on where its pending office actions are examined.

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