Listed by the USPTO as AISAKA, BRYCE M
Tech Center 2800 • Art Units: 1737 2825 2851
This examiner grants 88% of resolved cases
AISAKA, BRYCE M is a USPTO patent examiner in Tech Center 2800 and art unit 1737. The examiner has 753 resolved cases and an allowance rate of 87.5%, with a median of 855 days to allowance. The interview lift is 10.3%, indicating that interviews have a positive but limited association with allowance outcomes in the recorded cases.
The company list includes Taiwan Semiconductor Manufacturing Company, Ltd., Samsung Electronics Co., Ltd., and Intel Corporation. The listed firms are 2SPL Patent Attorneys, Arcane Law PLLC, and MERCHANT & GOULD P.C. For practitioners, the profile points to a substantial prosecution record and a company mix centered on semiconductor and electronics matters, while interview practice remains one consideration among several.
| App # | Title | Status | Assignee |
|---|---|---|---|
| 18404626 | METHOD FOR GENERATING LEARNING MODEL FOR PREDICTING SEMICONDUCTOR DEVICE STRUCTURE AND APPARATUS FOR PREDICTING SEMICONDUCTOR DEVICE STRUCTURE | Non-Final OA | SAMSUNG ELECTRONICS CO., LTD. |
| 18528501 | INTEGRATED CIRCUIT AND OPERATING METHOD THEREOF | Non-Final OA | SAMSUNG ELECTRONICS CO., LTD. |
| 18457619 | SERIES-CONNECTED BATTERY PACKS, SYSTEM AND METHOD | Final Rejection | MILWAUKEE ELECTRIC TOOL CORPORATION |
| 18395753 | DEVICE, METHOD, AND COMPUTER-READABLE MEDIUM FOR FORMAL VERIFICATION OF A CIRCUIT DESIGN | Non-Final OA | INTEL CORPORATION |
| 18215514 | CELL ROWS WITH MIXED HEIGHTS AND MIXED NANORIBBON WIDTHS | Non-Final OA | Intel Corporation |
| 18361532 | METHOD OF PREDICTING FAILURE IN A CIRCUIT DESIGN CAUSED BY NOISE IMPACT | Final Rejection | INTERNATIONAL BUSINESS MACHINES CORPORATION |
| 18545662 | I/O CIRCUIT, SEMICONDUCTOR DEVICE, CELL LIBRARY, AND METHOD OF DESIGNING CIRCUIT OF SEMICONDUCTOR DEVICE | Non-Final OA | ROHM CO., LTD. |
| 18408782 | DEVICE HAVING ALTERNATING ROWS OF CORRESPONDING FIRST AND SECOND ROW-ARCHITECTURES AND METHOD OF MANUFACTURING SAME | Non-Final OA | TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. |
| 18512411 | CONDUCTOR SCHEME SELECTION AND TRACK PLANNING FOR MIXED-DIAGONAL-MANHATTAN ROUTING | Non-Final OA | Taiwan Semiconductor Manufacturing Company, Ltd. |
| 18356408 | OPTIMIZED CELL LAYOUT | Non-Final OA | Taiwan Semiconductor Manufacturing Co., Ltd. |
| 18422939 | QUANTUM CIRCUIT DESIGNING APPARATUS AND METHOD | Non-Final OA | Seoul National University R&DB Foundation |
IP Author analyzes examiner patterns and generates tailored response strategies with the highest chance of allowance.
Build Your Strategy87.5% of resolved applications examined by Bryce M Aisaka were allowed (753 resolved cases), compared with 63.4% across Art Unit 1737 over the last five years.
This examiner's interview lift is +10.3 percentage points: the difference in allowance rate between resolved applications that had an examiner interview and those that did not.
Applications allowed by Bryce M Aisaka took 855 days on average from filing to allowance.
Bryce M Aisaka examines applications in Art Unit 1737 in Tech Center 2800 (Semiconductors, Circuits & Optics).
