Listed by the USPTO as CHEN, JACK S J
Tech Center 2800 • Art Units: 2893
This examiner grants 77% of resolved cases
CHEN, JACK S J is a USPTO patent examiner in tech center 2800 and art unit 2893. The record includes 578 resolved cases, an allowance rate of 76.6%, and a median of 1078 days to allowance. The interview lift is 5.9%, showing a relatively limited interview-associated difference within the broader allowance record.
The listed companies are STMicroelectronics N.V., Taiwan Semiconductor Manufacturing Company, Ltd., and Samsung Electronics Co., Ltd. The listed firms are Eschweiler & Potashnik, LLC (TSMC), Calderon Safran & Wright P.C., and HULTQUIST IP. Practitioners can use the profile to plan around the recorded allowance outcome and timing while calibrating expectations about interview impact.
| App # | Title | Status | Assignee |
|---|---|---|---|
| 18054970 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE INCLUDING TWO-DIMENSIONAL MATERIAL LAYER DEFINING AIR-GAP, AND SEMICONDUCTOR DEVICE | Non-Final OA | SAMSUNG ELECTRONICS CO., LTD. |
| 18466180 | VERTICAL GAN POWER TRANSISTOR UNIT CELL, VERTICAL GAN POWER TRANSISTOR AND METHOD FOR PRODUCING A VERTICAL GAN POWER TRANSISTOR UNIT CELL | Non-Final OA | Robert Bosch GmbH |
| 18463755 | SEMICONDUCTOR DEVICE | Non-Final OA | Toshiba Electronic Devices & Storage Corporation |
| 17919730 | ORGANIC SPACER FOR INTEGRATED CIRCUITS | Final Rejection | Intel NDTM US LLC |
| 18442416 | CRYSTAL CUTTING METHOD, METHOD OF MANUFACTURING SiC SEMICONDUCTOR DEVICE, AND SiC SEMICONDUCTOR DEVICE | Final Rejection | ROHM CO., LTD. |
| 18345767 | POWER MOSFET DEVICE WITH ISOLATED GATE STRUCTURE AND MANUFACTURING PROCESS THEREOF | Non-Final OA | STMICROELECTRONICS S.r.l. |
| 18324897 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES AND CORRESPONDING SEMICONDUCTOR DEVICE | Non-Final OA | STMICROELECTRONICS S.r.l. |
| 17941788 | SIC-BASED ELECTRONIC DEVICE WITH ENHANCED ROBUSTNESS, AND METHOD FOR MANUFACTURING THE ELECTRONIC DEVICE | Non-Final OA | STMICROELECTRONICS S.r.l. |
| 17592322 | VERTICAL CONDUCTION ELECTRONIC DEVICE COMPRISING A JBS DIODE AND MANUFACTURING PROCESS THEREOF | Final Rejection | STMicroelectronics S.r.l. |
| 17970327 | COOLING OF AN ELECTRONIC DEVICE | Final Rejection | STMICROELECTRONICS (GRENOBLE 2) SAS |
| 18321239 | FERROELECTRIC MEMORY DEVICE WITH SEMICONDUCTOR LAYER | Non-Final OA | Taiwan Semiconductor Manufacturing Company, Ltd. |
| 18316439 | THIN FILM TRANSISTOR STRUCTURE | Non-Final OA | Taiwan Semiconductor Manufacturing Company, Ltd. |
| 18613763 | THREE-DIMENSIONAL MEMORY DEVICE WITH SELF-ALIGNED WORD LINE CONTACT VIA STRUCTURES AND METHOD OF MAKING THE SAME | Non-Final OA | SANDISK TECHNOLOGIES LLC |
| 17808917 | DEPOSITION METHOD FOR FABRICATING SEMICONDUCTOR DEVICE STRUCTURE | Non-Final OA | NANYA TECHNOLOGY CORPORATION |
| 17951119 | HIGH ELECTRON MOBILITY TRANSISTOR AND METHOD FOR FABRICATING THE SAME | Final Rejection | UNITED MICROELECTRONICS CORP. |
| 17521076 | TRANSISTOR WITH FACETED, RAISED SOURCE/DRAIN REGION | Non-Final OA | GLOBALFOUNDRIES U.S. Inc. |
| 17950670 | Stress Management Layer for GaN HEMT | Non-Final OA | IQE plc |
IP Author analyzes examiner patterns and generates tailored response strategies with the highest chance of allowance.
Build Your Strategy76.6% of resolved applications examined by Jack S J Chen were allowed (578 resolved cases), compared with 79.0% across Art Unit 2893 over the last five years.
This examiner's interview lift is +5.9 percentage points: the difference in allowance rate between resolved applications that had an examiner interview and those that did not.
Applications allowed by Jack S J Chen took 1,078 days on average from filing to allowance.
Jack S J Chen examines applications in Art Unit 2893 in Tech Center 2800 (Semiconductors, Circuits & Optics).
