Listed by the USPTO as DYKES, LAURA M
Tech Center 2800 • Art Units: 2892
This examiner grants 66% of resolved cases
DYKES, LAURA M is a USPTO patent examiner in Tech Center 2800 and Art Unit 2892. The profile covers 530 resolved cases, with an allowance rate of 66.2% and an interview lift of 26.6%. The median time to allowance is 994 days. These figures provide a substantial case history for assessing prosecution outcomes and the potential value of interview-based engagement.
The listed companies include Samsung Electronics Co., Ltd., Samsung Display Co., Ltd., and Taiwan Semiconductor Manufacturing Company, Ltd. The listed firms are Muir Patent Law, PLLC, Womble Bond Dickinson US LLP, and BIRCH STEWART KOLASCH & BIRCH, LLP. Practitioners handling matters before this examiner can use the profile to frame expectations around allowance likelihood, timing, and interview strategy.
| App # | Title | Status | Assignee |
|---|---|---|---|
| 18922506 | SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR PACKAGE | Non-Final OA | Samsung Electronics Co., Ltd. |
| 18761886 | SEMICONDUCTOR DEVICE AND INTERCONNECTION STRUCTURE IN SEMICONDUCTOR DEVICE | Non-Final OA | Samsung Electronics Co., Ltd. |
| 18667670 | SEMICONDUCTOR PACKAGE | Non-Final OA | SAMSUNG ELECTRONICS CO.,LTD. |
| 18613471 | CAPACITOR STRUCTURE AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME | Non-Final OA | Samsung Electronics Co., Ltd. |
| 18771351 | Transparent Display Device | Non-Final OA | LG Display Co., Ltd. |
| 18531300 | Display Device and Method for Manufacturing the Same | Final Rejection | LG Display Co., Ltd. |
| 18827874 | FLEXIBLE CIRCUIT FILM AND DISPLAY APPARATUS HAVING SAME | Non-Final OA | Samsung Display Co., Ltd. |
| 18618854 | DISPLAY DEVICE | Final Rejection | Samsung Display Co., LTD. |
| 18382200 | DISPLAY PANEL AND ELECTRONIC APPARATUS INCLUDING THE SAME | Non-Final OA | Samsung Display Co., LTD. |
| 18476454 | DISPLAY MODULE AND MANUFACTURING METHOD FOR THE SAME | Final Rejection | Samsung Display Co., Ltd. |
| 18575411 | DISPLAY APPARATUS | Non-Final OA | Semiconductor Energy Laboratory Co., Ltd. |
| 18111525 | METHODS AND APPARATUS FOR STACKED DIE WARPAGE CONTROL DURING MASS REFLOW | Final Rejection | Micron Technology, Inc. |
| 18599586 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD | Non-Final OA | Kioxia Corporation |
| 18471223 | INTEGRATED STACKED SUBSTRATE FOR ISOLATED POWER MODULE | Non-Final OA | Texas Instruments Incorporated |
| 17946109 | WAFER BASED MOLDED FLIP CHIP ROUTABLE IC PACKAGE | Non-Final OA | Texas Instruments Incorporated |
| 18599771 | IMAGE SENSING DEVICE | Final Rejection | SK hynix Inc. |
| 18471219 | SIC-BASED ELECTRONIC DEVICE WITH IMPROVED BODY-SOURCE COUPLING, AND MANUFACTURING METHOD | Final Rejection | STMICROELECTRONICS S.r.l. |
| 18787569 | CAPACITOR IN NANOSHEET | Non-Final OA | Taiwan Semiconductor Manufacturing Company, Ltd. |
| 18618482 | SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME | Non-Final OA | Taiwan Semiconductor Manufacturing Company, Ltd. |
| 18581058 | SEMICONDUCTOR STRUCTURES FOR MONITORING PLASMA PROCESS-INDUCED DAMAGES | Non-Final OA | Taiwan Semiconductor Manufacturing Company, Ltd. |
| 18431950 | SEMICONDUCTOR DEVICES WITH LOWERED EPITAXIAL SOURCE/DRAIN REGIONS AND METHODS OF FABRICATION THEREOF | Non-Final OA | TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. |
| 18626389 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME | Non-Final OA | NANYA TECHNOLOGY CORPORATION |
| 18820928 | DEVICE CHIP MANUFACTURING METHOD | Non-Final OA | DISCO CORPORATION |
| 18581006 | CHIP CARRIER STRUCTURE | Final Rejection | SILICONWARE PRECISION INDUSTRIES CO., LTD. |
IP Author analyzes examiner patterns and generates tailored response strategies with the highest chance of allowance.
Build Your Strategy66.2% of resolved applications examined by Laura M Dykes were allowed (530 resolved cases), compared with 71.9% across Art Unit 2892 over the last five years.
This examiner's interview lift is +26.6 percentage points: the difference in allowance rate between resolved applications that had an examiner interview and those that did not.
Applications allowed by Laura M Dykes took 994 days on average from filing to allowance.
Laura M Dykes examines applications in Art Unit 2892 in Tech Center 2800 (Semiconductors, Circuits & Optics).
