Technology area: Semiconductors, Circuits & Optics
43 pending office actions • 1 client • 38 examiners • 20 art units • 0 of 43 (0%) have an AI response strategy ready
Dorsey & Whitney LLP - MTI (Nelson) has 44 pending office actions in Semiconductors, Circuits & Optics. The profile includes 15,565 career applications, providing a substantial historical context for the open prosecution activity.
The resolved allowance rate is 88.12%, and the average is 3.29 office actions per allowance. This indicates frequent allowance among resolved applications, but also shows that allowance generally followed multiple office-action cycles. Practitioners should separate current docket demands from historical results and examine how the recorded prosecution pattern applies to semiconductor, circuit, and optics claims.
Based on the USPTO statutory response window for each pending office action. 7 of the docket's apps have a known mailing date; the rest are excluded from the tile counts.
Every pending office action with a known statutory deadline, placed on a days-until-due axis. Dots left of Today are overdue; the further right, the more runway. Cases that share a deadline window stack vertically. 7 of the docket's apps have a known mailing date.
Difficulty is derived from the rejection statutes on the most recent pending office action. §101-driven and multi-statute cases are graded Hard; §112-only and obviousness-type double-patenting cases are graded Easy; everything else is Medium. "Unknown" means we have not yet parsed a statute for that office action.
| Bucket | Cases |
|---|---|
| §101 only | 1 (2%) |
| §103 only | 17 (40%) |
| §102 only | 4 (9%) |
| §112 only | 1 (2%) |
| Double-patenting only | 1 (2%) |
| Multi-statute (no §101) | 19 (44%) |
How the docket's pending cases split across USPTO tech-center bands.
Manual office-action response work runs about 10 hours per case. The time-saved bands below show what IP Author's prosecution pipeline typically delivers — a conservative 20% on the low end, 35% in the middle, 50% on the high end.
| Examiner | Apps on this docket | Allow rate | Interview lift |
|---|---|---|---|
| DAS, PINAKI | 3 | 87.5% | -1.9% |
| TURNER, BRIAN | 3 | 83.4% | +4.1% |
| GOODWIN, DAVID J | 2 | 67.2% | +16.7% |
| RIGOL, YAIMA | 1 | 75.6% | +17.4% |
| HUANG, MIN | 1 | 90.3% | +9.8% |
| LOTTICH, JOSHUA P | 1 | 90.3% | +3.4% |
| CHEN, XIAOCHUN L | 1 | 92.0% | -0.5% |
| SHAW, PETER C | 1 | 76.0% | +36.3% |
| AGGER, ELIZABETH ROSE | 1 | 95.2% | -0.9% |
| LUKE, DANIEL M | 1 | 71.4% | +18.7% |
Cases in front of an examiner with an allow rate of 80%+ where the difficulty is Easy or Medium. The top 4 ordered by deadline are shown.
| App # | Title | Examiner | Due in |
|---|---|---|---|
| 17874206 | HYBRID SEMICONDUCTOR DEVICE ASSEMBLY INTERCONNECTION PILLARS AND ASSOCIATED METHODS | DAS, PINAKI | 49d overdue |
| 18111424 | MODIFIED SEMICONDUCTOR DIE CARRIER AND CARRIER TAPE | TURNER, BRIAN | 23d |
| 17719241 | SEMICONDUCTOR DEVICE ASSEMBLIES INCLUDING MONOLITHIC SILICON STRUCTURES FOR THERMAL DISSIPATION AND METHODS OF MAKING THE SAME | DAS, PINAKI | — |
| 17587971 | STACKED SEMICONDUCTOR DIE ASSEMBLIES WITH HIGH EFFICIENCY THERMAL PATHS AND MOLDED UNDERFILL | TURNER, BRIAN | — |
Multi-statute / §101-driven matters, or cases in front of an examiner with an allow rate under 30%. The top 8 ordered by deadline are shown.
| App # | Title | Examiner | Due in |
|---|---|---|---|
| 17884484 | THROUGH-SUBSTRATE CONNECTIONS FOR RECESSED SEMICONDUCTOR DIES | WYATT, JOSHUA SCOTT | 46d overdue |
| 18111525 | METHODS AND APPARATUS FOR STACKED DIE WARPAGE CONTROL DURING MASS REFLOW | DYKES, LAURA M | 43d overdue |
| 17894063 | SEMICONDUCTOR PACKAGING WITH REDUCED STANDOFF HEIGHT | FAN, SU JYA | 42d overdue |
| 19094284 | APPARATUS INCLUDING MULTI-PURPOSE COMMUNICATION MECHANISM AND ASSOCIATED METHODS | HUANG, MIN | — |
| 19092944 | MEMORY SUB-SYSTEM WITH DYNAMIC CALIBRATION USING COMPONENT-BASED FUNCTION(S) | LOTTICH, JOSHUA P | — |
| 19069218 | MEMORY DEVICES WITH FINE-GRAINED COMMAND/ADDRESS TRAINING MODES | CHEN, XIAOCHUN L | — |
| 19044529 | SEMICONDUCTOR DEVICE WITH SELF-LOCK SECURITY AND ASSOCIATED METHODS AND SYSTEMS | SHAW, PETER C | — |
| 19029223 | METHODS FOR MITIGATING POWER LOSS EVENTS DURING OPERATION OF MEMORY DEVICES AND MEMORY DEVICES EMPLOYING THE SAME | AGGER, ELIZABETH ROSE | — |
Cases in front of an examiner whose interview lift is 10 percentage points or more — i.e. interviewed cases historically resolve more favorably than non-interviewed ones. The top 5 ordered by deadline are shown.
| App # | Title | Examiner | Due in |
|---|---|---|---|
| 19275605 | COMBINED MEMORY MODULE LOGIC DEVICES FOR REDUCED COST AND IMPROVED FUNCTIONALITY | RIGOL, YAIMA | — |
| 19044529 | SEMICONDUCTOR DEVICE WITH SELF-LOCK SECURITY AND ASSOCIATED METHODS AND SYSTEMS | SHAW, PETER C | — |
| 18827181 | BOND PAD WITH MICRO-PROTRUSIONS FOR DIRECT METALLIC BONDING | LUKE, DANIEL M | — |
| 18403007 | METHODS FOR MECHANICAL SELF-ALIGNMENT AND SLIP-RESISTANCE IN BONDING SEMICONDUCTOR SUBSTRATES, AND SEMICONDUCTOR DEVICES COMPRISING MECHANICAL SELF-ALIGNMENT STRUCTURES | GOODWIN, DAVID J | — |
| 17673309 | ELASTIC BONDING LAYERS FOR SEMICONDUCTOR DIE ASSEMBLIES AND ASSOCIATED SYSTEMS AND METHODS | GOODWIN, DAVID J | — |
| Client (Assignee) | Pending OAs |
|---|---|
| Micron | 43 |
| Art Unit | Apps |
|---|---|
| 2818 | 5 |
| 2893 | 4 |
| 2898 | 4 |
| 2899 | 4 |
| 2811 | 3 |
| 2892 | 3 |
| 2817 | 3 |
| 2824 | 2 |
| 2812 | 2 |
| 2814 | 2 |
| App # | Title | Client | Examiner | Art Unit | Statutes | Status | Due in | AI | Filed |
|---|---|---|---|---|---|---|---|---|---|
| 19275605 | COMBINED MEMORY MODULE LOGIC DEVICES FOR REDUCED COST AND IMPROVED FUNCTIONALITY | Micron Technology, Inc. | RIGOL, YAIMA | 2135 | DP | Final Rejection | — | Pending | Jul 21, 2025 |
| 19094284 | APPARATUS INCLUDING MULTI-PURPOSE COMMUNICATION MECHANISM AND ASSOCIATED METHODS | Micron Technology, Inc. | HUANG, MIN | §102§103 | Non-Final OA | — | Pending | Mar 28, 2025 | |
| 19092944 | MEMORY SUB-SYSTEM WITH DYNAMIC CALIBRATION USING COMPONENT-BASED FUNCTION(S) | Micron Technology, Inc. | LOTTICH, JOSHUA P | 2113 | §101 | Non-Final OA | — | Pending | Mar 27, 2025 |
| 19069218 | MEMORY DEVICES WITH FINE-GRAINED COMMAND/ADDRESS TRAINING MODES | Micron Technology, Inc. | CHEN, XIAOCHUN L | 2824 | §102§103 | Non-Final OA | — | Pending | Mar 04, 2025 |
| 19044529 | SEMICONDUCTOR DEVICE WITH SELF-LOCK SECURITY AND ASSOCIATED METHODS AND SYSTEMS | Micron Technology, Inc. | SHAW, PETER C | 2493 | §102§103Other | Non-Final OA | — | Pending | Feb 03, 2025 |
| 19029223 | METHODS FOR MITIGATING POWER LOSS EVENTS DURING OPERATION OF MEMORY DEVICES AND MEMORY DEVICES EMPLOYING THE SAME | Micron Technology, Inc. | AGGER, ELIZABETH ROSE | 2824 | §102§103§112 | Non-Final OA | — | Pending | Jan 17, 2025 |
| 18827181 | BOND PAD WITH MICRO-PROTRUSIONS FOR DIRECT METALLIC BONDING | Micron Technology, Inc. | LUKE, DANIEL M | 2896 | §103 | Non-Final OA | — | Pending | Sep 06, 2024 |
| 18788846 | SYSTEMS AND METHODS FOR MITIGATING CRACK MEANDERING IN SEMICONDUCTOR DICING | Micron Technology, Inc. | WATTS, JEREMY DANIEL | 2897 | §102§103 | Non-Final OA | — | Pending | Jul 30, 2024 |
| 18789665 | STORAGE OF DATA USING RETIRED MEMORY ROWS | Micron Technology, Inc. | BIRKHIMER, CHRISTOPHER D | 2138 | §103 | Non-Final OA | — | Pending | Jul 30, 2024 |
| 18787831 | FACE-TO-FACE SEMICONDUCTOR DEVICE WITH FAN-OUT PORCH | Micron Technology, Inc. | FERNANDES, ERROL V | 2893 | §102 | Non-Final OA | — | Pending | Jul 29, 2024 |
| 18782634 | LOW RESISTANCE ENHANCED ASPECT RATIO CONNECTOR FOR SEMICONDUCTOR DEVICE ASSEMBLY | Micron Technology, Inc. | RAMALLO, GUSTAVO G | 2812 | §102§103§112 | Non-Final OA | — | Pending | Jul 24, 2024 |
| 18774763 | LOW COST THREE-DIMENSIONAL STACKING SEMICONDUCTOR ASSEMBLIES | Micron Technology, Inc. | YUSHINA, GALINA G | 2811 | §103Other | Non-Final OA | — | Pending | Jul 16, 2024 |
| 18751061 | THERMAL PADS BETWEEN STACKED SEMICONDUCTOR DIES AND ASSOCIATED SYSTEMS AND METHODS | Micron Technology, Inc. | JONES, ERIC W | 2892 | §103§112 | Non-Final OA | — | Pending | Jun 21, 2024 |
| 18668134 | SEMICONDUCTOR DEVICES WITH A CURRENT GAIN LAYOUT | Micron Technology, Inc. | DINKE, BITEW A | 2812 | §102§103 | Non-Final OA | — | Pending | May 18, 2024 |
| 18667983 | SEMICONDUCTOR DEVICE WITH INTERCONNECTS FORMED THROUGH ATOMIC LAYER DEPOSITION | Micron Technology, Inc. | SCHOENHOLTZ, JOSEPH | 2893 | §102 | Non-Final OA | — | Pending | May 17, 2024 |
| 18668106 | METHOD OF MEASURING THICKNESS OF SEMICONDUCTOR WAFER AND INSPECTING BONDING VOIDS | Micron Technology, Inc. | DAS, PINAKI | 2898 | §103§112 | Non-Final OA | — | Pending | May 17, 2024 |
| 18652581 | PRINTED CIRCUIT BOARD WITH ENHANCED STRUCTURAL SUPPORT | Micron Technology, Inc. | TRAN, BINH BACH THANH | 2848 | §103 | Non-Final OA | — | Pending | May 01, 2024 |
| 18649297 | HIGH DENSITY PILLAR INTERCONNECT CONVERSION WITH STACK TO SUBSTRATE CONNECTION | Micron Technology, Inc. | GUMEDZOE, PENIEL M | 2899 | §102 | Non-Final OA | — | Pending | Apr 29, 2024 |
| 18619071 | SEMICONDUCTOR DEVICE WITH DUAL DAMASCENE AND DUMMY PADS | Micron Technology, Inc. | JOHNSON, CHRISTOPHER A | 2899 | §102§103§112 | Non-Final OA | — | Pending | Mar 27, 2024 |
| 18616019 | INDUCTORS WITH THROUGH-SUBSTRATE VIA CORES | Micron Technology, Inc. | LI, MEIYA | 2811 | §112 | Non-Final OA | — | Pending | Mar 25, 2024 |
| 18610268 | SEMICONDUCTOR DEVICE WITH A THROUGH DIELECTRIC VIA | Micron Technology, Inc. | HENRY, CALEB E | 2818 | §102 | Non-Final OA | — | Pending | Mar 20, 2024 |
| 18608868 | SEMICONDUCTOR ASSEMBLIES USING EDGE STACKING AND METHODS OF MANUFACTURING THE SAME | Micron Technology, Inc. | ELLIOTT, DANIEL KURT | 2899 | §102§103Other | Final Rejection | — | Pending | Mar 18, 2024 |
| 18605034 | THERMALLY REGULATED SEMICONDUCTOR DEVICE | Micron Technology, Inc. | LIU, BENJAMIN T | 2893 | §102§103 | Non-Final OA | — | Pending | Mar 14, 2024 |
| 18588352 | HIGH VOLTAGE DIODES FOR WAFER ON WAFER PACKAGING OF SEMICONDUCTOR DEVICE | Micron Technology, Inc. | HA, NATHAN W | 2814 | §103 | Non-Final OA | — | Pending | Feb 27, 2024 |
| 18426241 | STRING DRIVER WITH DEEP TRENCH ISOLATIONS | Micron Technology, Inc. | CHOUDHRY, MOHAMMAD M | 2899 | §103 | Non-Final OA | — | Pending | Jan 29, 2024 |
| 18410769 | SEMICONDUCTOR DEVICE WITH DELAMINATION REDUCTION MECHANISM AND METHODS FOR MANUFACTURING THE SAME | Micron Technology, Inc. | FREAL, JOHN BRENDAN | 2847 | §103 | Non-Final OA | — | Pending | Jan 11, 2024 |
| 18410808 | MEMORY DEVICE WITH 4N AND 8N DIE STACKS | Micron Technology, Inc. | LEE, CHUN KUAN | 2181 | §103 | Non-Final OA | — | Pending | Jan 11, 2024 |
| 18407428 | STACKED SEMICONDUCTOR DEVICE | Micron Technology, Inc. | BRECHT, CHARLES MATTHEW | 2817 | §102§103 | Non-Final OA | — | Pending | Jan 08, 2024 |
| 18403007 | METHODS FOR MECHANICAL SELF-ALIGNMENT AND SLIP-RESISTANCE IN BONDING SEMICONDUCTOR SUBSTRATES, AND SEMICONDUCTOR DEVICES COMPRISING MECHANICAL SELF-ALIGNMENT STRUCTURES | Micron Technology, Inc. | GOODWIN, DAVID J | 2817 | §103 | Non-Final OA | — | Pending | Jan 03, 2024 |
| 18505928 | SEMICONDUCTOR DEVICE ASSEMBLIES WITH AN ENCAPSULANT MATERIAL HAVING ENHANCED THERMAL CONDUCTIVITY, AND METHODS FOR MAKING THE SAME | Micron Technology, Inc. | GARCES, NELSON Y | 2814 | §103 | Final Rejection | — | Pending | Nov 09, 2023 |
| 18368449 | METHOD FOR SEMICONDUCTOR DIE EDGE PROTECTION AND SEMICONDUCTOR DIE SEPARATION | Micron Technology, Inc. | TURNER, BRIAN | 2818 | §102§103 | Final Rejection | — | Pending | Sep 14, 2023 |
| 18217827 | SEMICONDUCTOR DEVICE ASSEMBLIES WITH SCREEN-PRINTED EPOXY SPACERS AND METHODS FOR FORMING THE SAME | Micron Technology, Inc. | CUTLER, ETHAN EDWARD | 2892 | §103 | Non-Final OA | 70d | Pending | Jul 03, 2023 |
| 18111525 | METHODS AND APPARATUS FOR STACKED DIE WARPAGE CONTROL DURING MASS REFLOW | Micron Technology, Inc. | DYKES, LAURA M | 2892 | §103§112 | Final Rejection | 43d overdue | Pending | Feb 17, 2023 |
| 18111424 | MODIFIED SEMICONDUCTOR DIE CARRIER AND CARRIER TAPE | Micron Technology, Inc. | TURNER, BRIAN | 2818 | §103 | Non-Final OA | 23d | Pending | Feb 17, 2023 |
| 17894063 | SEMICONDUCTOR PACKAGING WITH REDUCED STANDOFF HEIGHT | Micron Technology, Inc. | FAN, SU JYA | 2818 | §102§103 | Non-Final OA | 42d overdue | Pending | Aug 23, 2022 |
| 17884484 | THROUGH-SUBSTRATE CONNECTIONS FOR RECESSED SEMICONDUCTOR DIES | Micron Technology, Inc. | WYATT, JOSHUA SCOTT | 2815 | §102§103§112 | Final Rejection | 46d overdue | Pending | Aug 09, 2022 |
| 17884468 | SEMICONDUCTOR DEVICE INTERCONNECTS HAVING CONDUCTIVE ANNULUS-STABILIZED THROUGH-SILICON VIAS | Micron Technology, Inc. | NADAV, ORI | 2811 | §103§112 | Non-Final OA | — | Pending | Aug 09, 2022 |
| 17874206 | HYBRID SEMICONDUCTOR DEVICE ASSEMBLY INTERCONNECTION PILLARS AND ASSOCIATED METHODS | Micron Technology, Inc. | DAS, PINAKI | 2898 | §103 | Non-Final OA | 49d overdue | Pending | Jul 26, 2022 |
| 17741200 | WAFER-LEVEL CHIP SCALE PACKAGING WITH COPPER CORE BALL EMBEDDED INTO MOLD | Micron Technology, Inc. | SCHODDE, CHRISTOPHER A | 2898 | §103§112 | Non-Final OA | — | Pending | May 10, 2022 |
| 17719241 | SEMICONDUCTOR DEVICE ASSEMBLIES INCLUDING MONOLITHIC SILICON STRUCTURES FOR THERMAL DISSIPATION AND METHODS OF MAKING THE SAME | Micron Technology, Inc. | DAS, PINAKI | 2898 | §103 | Final Rejection | — | Pending | Apr 12, 2022 |
| 17690981 | STRUCTURES AND METHODS FOR DICING SEMICONDUCTOR DEVICES | Micron Technology, Inc. | NETTLES, CORALIE ANN | 2893 | §103 | Final Rejection | 54d | Pending | Mar 09, 2022 |
| 17673309 | ELASTIC BONDING LAYERS FOR SEMICONDUCTOR DIE ASSEMBLIES AND ASSOCIATED SYSTEMS AND METHODS | Micron Technology, Inc. | GOODWIN, DAVID J | 2817 | §103 | Non-Final OA | — | Pending | Feb 16, 2022 |
| 17587971 | STACKED SEMICONDUCTOR DIE ASSEMBLIES WITH HIGH EFFICIENCY THERMAL PATHS AND MOLDED UNDERFILL | Micron Technology, Inc. | TURNER, BRIAN | 2818 | §103 | Non-Final OA | — | Pending | Jan 28, 2022 |
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Start Free Trial88.1% of resolved applications prosecuted by Dorsey & Whitney LLP - Mti (Nelson) were allowed, across 15,565 applications in USPTO records.
3.29 office actions per allowed application on average.
43 pending office actions as of October 2026, for 1 client, before 38 examiners in 20 art units.
