Prosecution Insights
Last updated: October 25, 2026

Etron Technology Inc.

Technology area: Semiconductors, Circuits & Optics

7 pending office actions • 6 art units • 6 examiners • 0 of 7 (0%) have an AI response strategy ready • 21 patents granted in the last 365 days

Analysis

Etron Technology Inc. has 7 pending office actions in Semiconductors, Circuits & Optics. The matters involve 6 distinct examiners and 6 distinct art units, indicating broad dispersion across both examiner and technical-unit assignments.

ZARNEKE, DAVID A is the busiest identified examiner, with 2 pending matters. Counsel should use consistent technical guidance while treating each art-unit and examiner relationship as a separate prosecution path.

Written from this page's own data; every figure is computed from USPTO records and verified before publication.

Portfolio Summary

7
Total Pending OAs
5
Non-Final OAs
2
Final Rejections
0
Advisory / Quayle

Response Deadline Pressure

Based on the USPTO statutory response window for each pending office action. 3 of the docket's apps have a known mailing date; the rest are excluded from the tile counts.

0
Overdue
0
Due this week
0
Due this month
1
Due in next 60 days
2
Due later

Deadline Fire Line

Every pending office action with a known statutory deadline, placed on a days-until-due axis. Dots left of Today are overdue; the further right, the more runway. Cases that share a deadline window stack vertically. 3 of the docket's apps have a known mailing date.

-30dToday30d60d90d120d
Due ≤ 60 days (1)Due later (2)

Case Difficulty Mix

Difficulty is derived from the rejection statutes on the most recent pending office action. §101-driven and multi-statute cases are graded Hard; §112-only and obviousness-type double-patenting cases are graded Easy; everything else is Medium. "Unknown" means we have not yet parsed a statute for that office action.

3
Hard (43%)
4
Medium (57%)
0
Easy (0%)
0
Unknown (0%)

Rejection Statute Mix

BucketCases
§103 only3 (43%)
Double-patenting + other1 (14%)
Multi-statute (no §101)3 (43%)

Industry Mix

How the docket's pending cases split across USPTO tech-center bands.

0
Life Sciences
0% of docket
1
Information Tech
14% of docket
0
Communications
0% of docket
6
Semiconductors
86% of docket
0
Mechanical / Eng
0% of docket
0
Business / Other
0% of docket

Time-on-OA Estimate

Manual office-action response work runs about 10 hours per case. The time-saved bands below show what IP Author's prosecution pipeline typically delivers — a conservative 20% on the low end, 35% in the middle, 50% on the high end.

70 h
Manual time on pending OAs
14 h
Time saved (low, 20%)
24 h
Time saved (mid, 35%)
0.6 wks
FTE-weeks freed (mid)

Top Examiners on this docket

ExaminerApps on this docketAllow rateInterview lift
ZARNEKE, DAVID A 2 71.1% +11.1%
WASSERBURG, DANIEL MORRIS 1 — —
NGUYEN, DUY T V 1 79.0% +16.7%
LEE, CHUN KUAN 1 68.4% +3.9%
KIELIN, ERIK J 1 67.7% +5.6%
WALL, VINCENT 1 62.6% +24.4%

Hard Cases (3)

Multi-statute / §101-driven matters, or cases in front of an examiner with an allow rate under 30%. The top 3 ordered by deadline are shown.

App #TitleExaminerDue in
18542032 SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING THE SAME WALL, VINCENT 75d
18785296 SEMICONDUCTOR DEVICE WASSERBURG, DANIEL MORRIS —
18634481 SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF MANUFACTURING THE SAME NGUYEN, DUY T V —

Interview Candidates (4)

Cases in front of an examiner whose interview lift is 10 percentage points or more — i.e. interviewed cases historically resolve more favorably than non-interviewed ones. The top 4 ordered by deadline are shown.

App #TitleExaminerDue in
18542032 SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING THE SAME WALL, VINCENT 75d
19214066 COWOS IC STRUCTURE WITH EDGE-PAD SEMICONDUCTOR DIE ZARNEKE, DAVID A 86d
19384467 3D INTEGRATED CIRCUIT PACKAGE ZARNEKE, DAVID A —
18634481 SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF MANUFACTURING THE SAME NGUYEN, DUY T V —

Top Art Units

Art UnitApps
2891 2
2892 1
2818 1
2181 1
2814 1
2898 1

Pending Office Actions

App #TitleExaminerArt UnitStatutesStatusDue inAIFiled
19384467 3D INTEGRATED CIRCUIT PACKAGE ZARNEKE, DAVID A 2891 §103DP Non-Final OA — Pending Nov 10, 2025
19214066 COWOS IC STRUCTURE WITH EDGE-PAD SEMICONDUCTOR DIE ZARNEKE, DAVID A 2891 §103 Final Rejection 86d Pending May 21, 2025
18785296 SEMICONDUCTOR DEVICE WASSERBURG, DANIEL MORRIS 2892 §102§103 Non-Final OA — Pending Jul 26, 2024
18634481 SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF MANUFACTURING THE SAME NGUYEN, DUY T V 2818 §102§103 Non-Final OA — Pending Apr 12, 2024
18600820 MEMORY SYSTEM AND MEMORY CHIP LEE, CHUN KUAN 2181 §103 Non-Final OA 46d Pending Mar 11, 2024
18592521 SEMICONDUCTOR PACKAGE FOR LIQUID IMMERSION COOLING AND METHOD OF FORMING THE SAME KIELIN, ERIK J 2814 §103 Non-Final OA — Pending Mar 01, 2024
18542032 SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING THE SAME WALL, VINCENT 2898 §102§103 Final Rejection 75d Pending Dec 15, 2023

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Frequently Asked Questions

How many pending USPTO office actions does Etron Technology Inc. have?

Etron Technology Inc. has 7 pending office actions as of October 2026, spread across 6 art units and 6 examiners.

Which USPTO examiner handles the most Etron Technology Inc. applications?

David A Zarneke has the most, with 2 of Etron Technology Inc.'s pending office actions.

What technology area are Etron Technology Inc.'s patent applications in?

Mostly Semiconductors, Circuits & Optics (USPTO Tech Center 2800), based on where its pending office actions are examined.

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