Listed by the USPTO as JAGER, RYAN C
Tech Center 2800 • Art Units: 2434 2816 2836 2842
This examiner grants 90% of resolved cases
JAGER, RYAN C is a USPTO patent examiner in Tech Center 2800 and Art Unit 2434. The record includes 941 resolved cases, an allowance rate of 89.6%, and a median of 704 days to allowance. The interview lift is 3.0%, indicating a positive interview metric but a limited reported effect within this profile.
The listed companies are Taiwan Semiconductor Manufacturing Company, Ltd., Samsung Electronics Co., Ltd., and Innolux Corporation. The listed firms are AMIN, TUROCY & WATSON, LLP, AMPACC Law Group, PLLC, and BIRCH STEWART KOLASCH & BIRCH, LLP. The 89.6% allowance rate and 704-day median provide clear outcome and duration references. The 3.0% interview lift supports treating interviews as an available tool, while the broader allowance result remains the principal profile indicator.
| App # | Title | Status | Assignee |
|---|---|---|---|
| 19056705 | APPARATUS, SYSTEM, AND METHOD WITH SUPERCONDUCTING QUANTUM CIRCUIT | Non-Final OA | Samsung Electronics Co., Ltd. |
| 18632231 | ELECTRONIC CIRCUIT | Final Rejection | Innolux Corporation |
| 19231290 | ELECTROSTATIC DISCHARGE CIRCUIT AND ELECTROSTATIC DISCHARGE CONTROL SYSTEM | Non-Final OA | SK hynix Inc. |
| 19252413 | GATED TRI-STATE INVERTER, AND METHOD OF OPERATING SAME | Non-Final OA | TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. |
| 19214788 | Pulse Width Control Apparatus and Method | Non-Final OA | Taiwan Semiconductor Manufacturing Company, Ltd. |
| 19200973 | SYSTEM AND SEMICONDUCTOR DEVICE THEREIN | Non-Final OA | TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. |
| 18878356 | ELECTRICAL ASSEMBLY COMPRISING A VOLTAGE SOURCE CONVERTER AND AN ENERGY STORAGE SYSTEM | Non-Final OA | GE Infrastructure Technology LLC |
| 19013962 | MONOLITHICALLY INTEGRATED CHALCOGENIDE SWITCH MATRIX | Final Rejection | Dell Products L.P. |
IP Author analyzes examiner patterns and generates tailored response strategies with the highest chance of allowance.
Build Your Strategy89.6% of resolved applications examined by Ryan C Jager were allowed (941 resolved cases), compared with 76.5% across Art Unit 2434 over the last five years.
This examiner's interview lift is +3.0 percentage points: the difference in allowance rate between resolved applications that had an examiner interview and those that did not.
Applications allowed by Ryan C Jager took 704 days on average from filing to allowance.
Ryan C Jager examines applications in Art Unit 2434 in Tech Center 2800 (Semiconductors, Circuits & Optics).
