Listed by the USPTO as JEAN BAPTISTE, WILNER
Tech Center 2800 • Art Units: 2823 2897 2899
This examiner grants 87% of resolved cases
JEAN BAPTISTE, WILNER is assigned to tech center 2800 and art unit 2823. The profile covers 1109 resolved cases, with an 86.6% allowance rate and a median of 836 days to allowance. Its 5.2% interview lift indicates a limited interview-associated change relative to the overall allowance result. Applicants can use this record to set expectations about duration while emphasizing claim clarity and written prosecution strategy.
The listed companies are Taiwan Semiconductor Manufacturing Company, Ltd., LG Electronics Inc., and Sony Group Corporation. The associated firms are Alliance IP, LLC - Intel, CKC & Partners Co., LLC, and FITCH, EVEN, TABIN & FLANNERY, LLP. These histories offer relevant examples for semiconductor and electronics claim prosecution in art unit 2823.
| App # | Title | Status | Assignee |
|---|---|---|---|
| 18729357 | X-RAY DETECTOR COMPRISING SCINTILLATOR, WHICH COMPRISES PEROVSKITE COMPOUND | Non-Final OA | LG ELECTRONICS INC. |
| 18716464 | SEMICONDUCTOR DEVICE, ELECTRONIC EQUIPMENT, AND WAFER | Non-Final OA | SONY SEMICONDUCTOR SOLUTIONS CORPORATION |
| 18061283 | INTEGRATED CIRCUIT PACKAGE ARCHITECTURES WITH CORE AND/OR BUILD-UP LAYERS COMPRISING SPIN-ON GLASS (SOG) | Final Rejection | Intel Corporation |
| 18412458 | LASER PROCESSING APPARATUS AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE | Final Rejection | Mitsubishi Electric Corporation |
| 18778329 | Integrated Circuitry, Memory Circuitry, And Method Of Forming Integrated Circuitry | Non-Final OA | Micron Technology, Inc. |
| 18414003 | SILICON NITRIDE METAL LAYER COVERS | Final Rejection | TEXAS INSTRUMENTS INCORPORATED |
| 18480143 | NANOSHEET TRANSISTORS WITH MULTI-LAYERED CHANNEL STRUCTURES | Non-Final OA | International Business Machines Corporation |
| 18732621 | SEMICONDUCTOR DEVICE INCLUDING RESONANT TUNNELING LAYER | Non-Final OA | SK hynix Inc. |
| 18731821 | BONDED STRUCTURE WITH HALF-OVAL BONDING PAD PAIR DESIGN AND METHOD OF FORMING THE SAME | Non-Final OA | Taiwan Semiconductor Manufacturing Company, Ltd. |
| 18398856 | SEMICONDUCTOR MEMORY CELL STRUCTURE INCLUDING A VERTICAL CHANNEL | Non-Final OA | Taiwan Semiconductor Manufacturing Company, Ltd. |
| 18785335 | DIE ON DIE BONDING STRUCTURE | Non-Final OA | Taiwan Semiconductor Manufacturing Co., Ltd. |
| 18782354 | HETEROGENOUS INTEGRATION SCHEME FOR III-V/Si AND Si CMOS INTEGRATED CIRCUITS | Non-Final OA | Taiwan Semiconductor Manufacturing Co., Ltd. |
| 18729041 | SEMICONDUCTOR PACKAGE AND SEMICONDUCTOR DEVICE | Non-Final OA | Resonac Corporation |
IP Author analyzes examiner patterns and generates tailored response strategies with the highest chance of allowance.
Build Your Strategy86.6% of resolved applications examined by Wilner Jean Baptiste were allowed (1,109 resolved cases), compared with 46.2% across Art Unit 2823 over the last five years.
This examiner's interview lift is +5.2 percentage points: the difference in allowance rate between resolved applications that had an examiner interview and those that did not.
Applications allowed by Wilner Jean Baptiste took 836 days on average from filing to allowance.
Wilner Jean Baptiste examines applications in Art Unit 2823 in Tech Center 2800 (Semiconductors, Circuits & Optics).
