Listed by the USPTO as LE, THAO P
Tech Center 2800 • Art Units: 2818 2831
This examiner grants 92% of resolved cases
| App # | Title | Status | Assignee |
|---|---|---|---|
| 18825437 | SEMICONDUCTOR DEVICE AND DATA STORAGE SYSTEM INCLUDING THE SAME | Non-Final OA | Samsung Electronics Co., Ltd. |
| 18788803 | HYBRID ELEMENT AND METHOD OF FABRICATING THE SAME | Non-Final OA | Samsung Electronics Co., Ltd. |
| 18396340 | CHIP PACKAGING METHOD AND CHIP PACKAGE BASED ON PANEL FORM | Non-Final OA | SAMSUNG ELECTRONICS CO., LTD. |
| 18611442 | ELECTRONIC DEVICE AND METHOD OF MANUFACTURING THE SAME | Non-Final OA | Samsung Display Co., Ltd. |
| 18712265 | Display Panel and Preparation Method Therefor, and Display Apparatus | Non-Final OA | BOE Technology Group Co., Ltd. |
| 18542156 | PACKAGING FOR MICRO-ELECTROMECHANICAL SYSTEM (MEMS) DEVICE | Non-Final OA | QUALCOMM Incorporated |
| 18644145 | ELECTRONIC DEVICE AND TILED ELECTRONIC DEVICE | Non-Final OA | Innolux Corporation |
| 18690472 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME | Non-Final OA | Mitsubishi Electric Corporation |
| 18690574 | OVERHANG PATTERN FOR ADVANCED OLED PATTERNING | Non-Final OA | Applied Materials, Inc. |
| 18784544 | CHANNEL LAST PROCESS FOR DUMMY GATE VOID DEFECT REDUCTION | Non-Final OA | Taiwan Semiconductor Manufacturing Company, Ltd. |
| 18773592 | MANUFACTURING METHOD OF PACKAGE STRUCTURE | Non-Final OA | Taiwan Semiconductor Manufacturing Company, Ltd. |
| 18768421 | VERTICAL INTERCONNECT STRUCTURES WITH INTEGRATED CIRCUITS | Non-Final OA | Taiwan Semiconductor Manufacturing Company, Ltd. |
| 18308866 | CHIP PACKAGE STRUCTURE WITH ANTI-WARPAGE STRUCTURE AND METHOD FOR FORMING THE SAME | Non-Final OA | Taiwan Semiconductor Manufacturing Company, Ltd. |
| 18771613 | THREE-DIMENSIONAL DEVICE STRUCTURE INCLUDING EMBEDDED INTEGRATED PASSIVE DEVICE AND METHODS OF MAKING THE SAME | Non-Final OA | Taiwan Semiconductor Manufacturing Company Limited |
IP Author analyzes examiner patterns and generates tailored response strategies with the highest chance of allowance.
Build Your Strategy92.5% of resolved applications examined by Thao P Le were allowed (818 resolved cases), compared with 85.2% across Art Unit 2818 over the last five years.
This examiner's interview lift is -0.8 percentage points: the difference in allowance rate between resolved applications that had an examiner interview and those that did not.
Applications allowed by Thao P Le took 671 days on average from filing to allowance.
Thao P Le examines applications in Art Unit 2818 in Tech Center 2800 (Semiconductors, Circuits & Optics).
