Listed by the USPTO as LI, MEIYA
Tech Center 2800 • Art Units: 2800 2811
This examiner grants 69% of resolved cases
LI, MEIYA works in Tech Center 2800 and Art Unit 2800. Her profile records 948 resolved cases, a 69.1% allowance rate, and a median of 1315 days to allowance. The interview lift is 26.0%, supporting use of interviews when counsel can present focused technical or claim-based distinctions.
The principal companies are Taiwan Semiconductor Manufacturing Company, Ltd., Samsung Electronics Co., Ltd., and NANYA TECHNOLOGY Corporation. The leading firms are BIRCH STEWART KOLASCH & BIRCH, LLP, DINSMORE & SHOHL LLP, and Dorsey & Whitney LLP - MTI (Nelson). The substantial record supports meaningful planning, while the median timing calls for sustained docket attention.
| App # | Title | Status | Assignee |
|---|---|---|---|
| 18628890 | SEMICONDUCTOR PACKAGE AND WIRING SUBSTRATE USED FOR THE SAME | Non-Final OA | SAMSUNG ELECTRONICS CO., LTD. |
| 18386429 | VERTICAL MEMORY DEVICES INCLUDING DIVISION PATTERNS | Non-Final OA | SAMSUNG ELECTRONICS CO., LTD. |
| 14942170 | ENHANCEMENT OF ORGANIC PHOTOVOLTAIC CELL OPEN CIRCUIT VOLTAGE USING ELECTRON/HOLE BLOCKING EXCITON BLOCKING LAYERS | Final Rejection | THE REGENTS OF THE UNIVERSITY OF MICHIGAN |
| 18616019 | INDUCTORS WITH THROUGH-SUBSTRATE VIA CORES | Non-Final OA | Micron Technology, Inc. |
| 18592970 | SEMICONDUCTOR DEVICE | Non-Final OA | Kioxia Corporation |
| 18233697 | THREE-DIMENSIONAL MEMORY DEVICE INCLUDING A METAL OXIDE ETCH STOP LAYER AND METHODS FOR FORMING THE SAME | Non-Final OA | WESTERN DIGITAL TECHNOLOGIES, INC. |
| 18111577 | High Voltage Blocking III-V Semiconductor Device | Final Rejection | Infineon Technologies Austria AG |
| 18788741 | Radical Treatment in Supercritical Fluid for Gate Dielectric Quality Improvement to CFET Structure | Non-Final OA | Taiwan Semiconductor Manufacturing Company, Ltd. |
| 17335985 | SEMICONDUCTOR PACKAGE AND METHOD OF MAKING | Final Rejection | TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. |
| 18591792 | FORMING ISOLATION REGIONS WITH LOW PARASITIC CAPACITANCE AND REDUCED DAMAGE | Non-Final OA | Taiwan Semiconductor Manufacturing Co., Ltd. |
| 18412779 | SEMICONDUCTOR PACKAGE STRUCTURES AND METHODS OF FORMING SAME | Non-Final OA | Taiwan Semiconductor Manufacturing Co., Ltd. |
| 18446753 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF | Final Rejection | TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. |
| 17845849 | METHOD FOR PREPARING MEMORY DEVICE WITH MULTILAYERED CAPACITOR DIELECTRIC STRUCTURE | Final Rejection | NANYA TECHNOLOGY CORPORATION |
| 17741593 | MEMORY DEVICE HAVING PROTRUDING CHANNEL STRUCTURE | Final Rejection | NANYA TECHNOLOGY CORPORATION |
IP Author analyzes examiner patterns and generates tailored response strategies with the highest chance of allowance.
Build Your Strategy69.1% of resolved applications examined by Meiya Li were allowed (948 resolved cases), compared with 69.7% across Art Unit 2800 over the last five years.
This examiner's interview lift is +26.0 percentage points: the difference in allowance rate between resolved applications that had an examiner interview and those that did not.
Applications allowed by Meiya Li took 1,315 days on average from filing to allowance.
Meiya Li examines applications in Art Unit 2800 in Tech Center 2800 (Semiconductors, Circuits & Optics).
