Listed by the USPTO as MOTT, ADAM JOSEPH
Tech Center 2800 • Art Units: 2817
This examiner grants 97% of resolved cases
| App # | Title | Status | Assignee |
|---|---|---|---|
| 18754605 | SEMICONDUCTOR PACKAGE | Non-Final OA | SAMSUNG ELECTRONICS CO., LTD. |
| 18334100 | METHOD FOR MANUFACTURING SEMICONDUCTOR PACKAGE USING SACRIFICIAL LAYER AND SEMICONDUCTOR PACKAGE MANUFACTURED BY USING THEREOF | Final Rejection | SAMSUNG ELECTRONICS CO., LTD. |
| 18559958 | TUNGSTEN WORDLINE FILL IN HIGH ASPECT RATIO 3D NAND ARCHITECTURE | Non-Final OA | Lam Research Corporation |
| 18365259 | SEMICONDUCTOR PACKAGE ASSEMBLY | Non-Final OA | MEDIATEK INC. |
IP Author analyzes examiner patterns and generates tailored response strategies with the highest chance of allowance.
Build Your Strategy97.0% of resolved applications examined by Adam Joseph Mott were allowed (33 resolved cases), compared with 81.7% across Art Unit 2817 over the last five years.
This examiner's interview lift is -12.5 percentage points: the difference in allowance rate between resolved applications that had an examiner interview and those that did not.
Applications allowed by Adam Joseph Mott took 1,178 days on average from filing to allowance.
Adam Joseph Mott examines applications in Art Unit 2817 in Tech Center 2800 (Semiconductors, Circuits & Optics).
