Technology area: Semiconductors, Circuits & Optics
8 pending office actions • 3 art units • 7 examiners • 0 of 8 (0%) have an AI response strategy ready • 5 patents granted in the last 365 days
Invention And Collaboration Laboratory Inc. manages 7 pending office actions within the Semiconductors, Circuits & Optics technology area. These actions are distributed among 6 distinct examiners, showing that applications are being reviewed by different individuals. This spread allows the company to receive varied feedback across its pending semiconductor portfolio.
The 7 pending office actions are concentrated within 3 distinct art units. This suggests that while the company interacts with 6 distinct examiners, those examiners are grouped into a small number of specialized units. This concentration in 3 art units may allow for a more unified prosecution strategy within those specific technical domains.
The busiest examiner, RODELA, EDUARDO A, is currently responsible for 2 pending office actions. This represents the highest level of examiner concentration in the portfolio, though it still only accounts for 2 of the 7 pending office actions. Practitioners should note that the workload is spread across 6 distinct examiners, requiring a strategy that accounts for multiple individual perspectives.
Based on the USPTO statutory response window for each pending office action. 1 of the docket's apps have a known mailing date; the rest are excluded from the tile counts.
Difficulty is derived from the rejection statutes on the most recent pending office action. §101-driven and multi-statute cases are graded Hard; §112-only and obviousness-type double-patenting cases are graded Easy; everything else is Medium. "Unknown" means we have not yet parsed a statute for that office action.
| Bucket | Cases |
|---|---|
| §103 only | 3 (38%) |
| Multi-statute (no §101) | 5 (62%) |
How the docket's pending cases split across USPTO tech-center bands.
Manual office-action response work runs about 10 hours per case. The time-saved bands below show what IP Author's prosecution pipeline typically delivers — a conservative 20% on the low end, 35% in the middle, 50% on the high end.
| Examiner | Apps on this docket | Allow rate | Interview lift |
|---|---|---|---|
| RODELA, EDUARDO A | 2 | 86.3% | +5.8% |
| HUTSON, NICHOLAS LELAND | 1 | 68.8% | +6.1% |
| ZABEL, ANDREW JOHN | 1 | 82.5% | +25.9% |
| DANG, PHUC T | 1 | 95.5% | +1.4% |
| STARK, JARRETT J | 1 | 70.4% | +11.0% |
| BODNAR, JOHN A | 1 | 83.0% | +12.2% |
| WOLDEGEORGIS, ERMIAS T | 1 | 70.9% | +12.1% |
Cases in front of an examiner with an allow rate of 80%+ where the difficulty is Easy or Medium. The top 3 ordered by deadline are shown.
| App # | Title | Examiner | Due in |
|---|---|---|---|
| 18736565 | COMPLEMENTARY METAL-OXIDE-SEMICONDUCTOR CIRCUIT | DANG, PHUC T | — |
| 18662717 | PLANAR COMPLEMENTARY MOSFET STRUCTURE TO REDUCE LEAKAGES AND PLANAR AREAS | RODELA, EDUARDO A | — |
| 18422360 | PLANAR COMPLEMENTARY MOSFET STRUCTURE TO REDUCE LEAKAGES AND PLANAR AREAS | RODELA, EDUARDO A | — |
Multi-statute / §101-driven matters, or cases in front of an examiner with an allow rate under 30%. The top 5 ordered by deadline are shown.
| App # | Title | Examiner | Due in |
|---|---|---|---|
| 18533720 | SEMICONDUCTOR DEVICE STRUCTURE WITH EFFICIENT HEAT-REMOVAL STRUCTURES ACROSS THE CHIP AND MONOLITHIC FABRICATION METHOD THEREFOR | WOLDEGEORGIS, ERMIAS T | 22d overdue |
| 18815258 | SEMICONDUCTOR PACKAGE STRUCTURE FOR ENHANCED COOLING | HUTSON, NICHOLAS LELAND | — |
| 18757552 | SEMICONDUCTOR STRUCTURE | ZABEL, ANDREW JOHN | — |
| 18662141 | SEMICONDUCTOR CIRCUIT STRUCTURE WITH DIRECT DIE HEAT REMOVAL STRUCTURE | STARK, JARRETT J | — |
| 18599239 | metal-oxide-semiconductor transistor and complementary metal-oxide-semiconductor circuit related | BODNAR, JOHN A | — |
Cases in front of an examiner whose interview lift is 10 percentage points or more — i.e. interviewed cases historically resolve more favorably than non-interviewed ones. The top 4 ordered by deadline are shown.
| App # | Title | Examiner | Due in |
|---|---|---|---|
| 18533720 | SEMICONDUCTOR DEVICE STRUCTURE WITH EFFICIENT HEAT-REMOVAL STRUCTURES ACROSS THE CHIP AND MONOLITHIC FABRICATION METHOD THEREFOR | WOLDEGEORGIS, ERMIAS T | 22d overdue |
| 18757552 | SEMICONDUCTOR STRUCTURE | ZABEL, ANDREW JOHN | — |
| 18662141 | SEMICONDUCTOR CIRCUIT STRUCTURE WITH DIRECT DIE HEAT REMOVAL STRUCTURE | STARK, JARRETT J | — |
| 18599239 | metal-oxide-semiconductor transistor and complementary metal-oxide-semiconductor circuit related | BODNAR, JOHN A | — |
| Art Unit | Apps |
|---|---|
| 2893 | 4 |
| 2818 | 2 |
| 2898 | 1 |
| App # | Title | Examiner | Art Unit | Statutes | Status | Due in | AI | Filed |
|---|---|---|---|---|---|---|---|---|
| 18815258 | SEMICONDUCTOR PACKAGE STRUCTURE FOR ENHANCED COOLING | HUTSON, NICHOLAS LELAND | 2818 | §103§112 | Non-Final OA | — | Pending | Aug 26, 2024 |
| 18757552 | SEMICONDUCTOR STRUCTURE | ZABEL, ANDREW JOHN | 2818 | §102§103 | Non-Final OA | — | Pending | Jun 28, 2024 |
| 18736565 | COMPLEMENTARY METAL-OXIDE-SEMICONDUCTOR CIRCUIT | DANG, PHUC T | — | §103 | Non-Final OA | — | Pending | Jun 07, 2024 |
| 18662717 | PLANAR COMPLEMENTARY MOSFET STRUCTURE TO REDUCE LEAKAGES AND PLANAR AREAS | RODELA, EDUARDO A | 2893 | §103 | Non-Final OA | — | Pending | May 13, 2024 |
| 18662141 | SEMICONDUCTOR CIRCUIT STRUCTURE WITH DIRECT DIE HEAT REMOVAL STRUCTURE | STARK, JARRETT J | 2898 | §102§103 | Non-Final OA | — | Pending | May 13, 2024 |
| 18599239 | metal-oxide-semiconductor transistor and complementary metal-oxide-semiconductor circuit related | BODNAR, JOHN A | 2893 | §102§103§112 | Final Rejection | — | Pending | Mar 08, 2024 |
| 18422360 | PLANAR COMPLEMENTARY MOSFET STRUCTURE TO REDUCE LEAKAGES AND PLANAR AREAS | RODELA, EDUARDO A | 2893 | §103 | Non-Final OA | — | Pending | Jan 25, 2024 |
| 18533720 | SEMICONDUCTOR DEVICE STRUCTURE WITH EFFICIENT HEAT-REMOVAL STRUCTURES ACROSS THE CHIP AND MONOLITHIC FABRICATION METHOD THEREFOR | WOLDEGEORGIS, ERMIAS T | 2893 | §102§103 | Non-Final OA | 22d overdue | Pending | Dec 08, 2023 |
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Start Free TrialInvention And Collaboration Laboratory Inc. has 8 pending office actions as of October 2026, spread across 3 art units and 7 examiners.
Eduardo A Rodela has the most, with 2 of Invention And Collaboration Laboratory Inc.'s pending office actions.
Mostly Semiconductors, Circuits & Optics (USPTO Tech Center 2800), based on where its pending office actions are examined.
