Prosecution Insights
Last updated: October 02, 2026

Toyota Tsusho Corporation

Technology areas: Chemistry & Materials • Semiconductors, Circuits & Optics

3 pending office actions • 2 art units • 2 examiners • 0 of 3 (0%) have an AI response strategy ready • 12 patents granted in the last 365 days

Analysis

Toyota Tsusho Corporation has 3 pending office actions in the Semiconductors, Circuits & Optics technology area. These actions are handled by 2 distinct examiners across 2 distinct art units. This distribution indicates a slight concentration of the company's workload, as the number of actions exceeds the number of examiners and art units involved.

QI, HUA is the busiest examiner for this portfolio, holding 2 busiest examiner pending actions. This means that QI, HUA is responsible for the majority of the company's current pending matters. The remaining action is handled by the other of the 2 distinct examiners. This concentration with QI, HUA in the Semiconductors, Circuits & Optics area suggests that the company's success in this technology space is currently heavily influenced by a single reviewer. Practitioners should prioritize understanding the specific tendencies of QI, HUA, while also managing the 2 distinct art units where these applications are being examined.

Written from this page's own data; every figure is computed from USPTO records and verified before publication.

Portfolio Summary

3
Total Pending OAs
2
Non-Final OAs
1
Final Rejections
0
Advisory / Quayle

Response Deadline Pressure

Based on the USPTO statutory response window for each pending office action. 1 of the docket's apps have a known mailing date; the rest are excluded from the tile counts.

1
Overdue
0
Due this week
0
Due this month
0
Due in next 60 days
0
Due later

Case Difficulty Mix

Difficulty is derived from the rejection statutes on the most recent pending office action. §101-driven and multi-statute cases are graded Hard; §112-only and obviousness-type double-patenting cases are graded Easy; everything else is Medium. "Unknown" means we have not yet parsed a statute for that office action.

3
Hard (100%)
0
Medium (0%)
0
Easy (0%)
0
Unknown (0%)

Rejection Statute Mix

BucketCases
Multi-statute (no §101)3 (100%)

Industry Mix

How the docket's pending cases split across USPTO tech-center bands.

1
Life Sciences
33% of docket
0
Information Tech
0% of docket
0
Communications
0% of docket
1
Semiconductors
33% of docket
0
Mechanical / Eng
0% of docket
1
Business / Other
33% of docket

Time-on-OA Estimate

Manual office-action response work runs about 10 hours per case. The time-saved bands below show what IP Author's prosecution pipeline typically delivers — a conservative 20% on the low end, 35% in the middle, 50% on the high end.

30 h
Manual time on pending OAs
6 h
Time saved (low, 20%)
10 h
Time saved (mid, 35%)
0.3 wks
FTE-weeks freed (mid)

Top Examiners on this docket

ExaminerApps on this docketAllow rateInterview lift
QI, HUA 2 56.6% +23.1%
COOK, JONATHON 1 81.6% +17.0%

Hard Cases (3)

Multi-statute / §101-driven matters, or cases in front of an examiner with an allow rate under 30%. The top 3 ordered by deadline are shown.

App #TitleExaminerDue in
17763684 METHOD FOR PRODUCING SEMICONDUCTOR SUBSTRATES AND DEVICE FOR PRODUCING SEMICONDUCTOR SUBSTRATES QI, HUA 18d overdue
18840885 METHOD FOR SUPPRESSING FORMATION OF STACKING FAULT, STRUCTURE PRODUCED BY THIS METHOD, AND METHOD FOR EVALUATING AFFECTED LAYER QI, HUA —
18261101 METHOD AND SYSTEM FOR EVALUATING WORK-AFFECTED LAYER COOK, JONATHON —

Interview Candidates (3)

Cases in front of an examiner whose interview lift is 10 percentage points or more — i.e. interviewed cases historically resolve more favorably than non-interviewed ones. The top 3 ordered by deadline are shown.

App #TitleExaminerDue in
17763684 METHOD FOR PRODUCING SEMICONDUCTOR SUBSTRATES AND DEVICE FOR PRODUCING SEMICONDUCTOR SUBSTRATES QI, HUA 18d overdue
18840885 METHOD FOR SUPPRESSING FORMATION OF STACKING FAULT, STRUCTURE PRODUCED BY THIS METHOD, AND METHOD FOR EVALUATING AFFECTED LAYER QI, HUA —
18261101 METHOD AND SYSTEM FOR EVALUATING WORK-AFFECTED LAYER COOK, JONATHON —

Top Art Units

Art UnitApps
2877 1
1714 1

Pending Office Actions

App #TitleExaminerArt UnitStatutesStatusDue inAIFiled
18840885 METHOD FOR SUPPRESSING FORMATION OF STACKING FAULT, STRUCTURE PRODUCED BY THIS METHOD, AND METHOD FOR EVALUATING AFFECTED LAYER QI, HUA — §102§103 Non-Final OA — Pending Aug 22, 2024
18261101 METHOD AND SYSTEM FOR EVALUATING WORK-AFFECTED LAYER COOK, JONATHON 2877 §102§103§112 Non-Final OA — Pending Jul 11, 2023
17763684 METHOD FOR PRODUCING SEMICONDUCTOR SUBSTRATES AND DEVICE FOR PRODUCING SEMICONDUCTOR SUBSTRATES QI, HUA 1714 §103§112 Final Rejection 18d overdue Pending Mar 25, 2022

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