Prosecution Insights
Last updated: October 25, 2026

Essential Patents Group, Llp.

Technology area: Semiconductors, Circuits & Optics

79 pending office actions • 1 client • 76 examiners • 39 art units • 29 of 79 (37%) have an AI response strategy ready

Analysis

Essential Patents Group, LLP. handles matters in Semiconductors, Circuits & Optics and records 2866 career applications. Its profile shows 75 pending office actions, reflecting a significant active docket supported by a substantial application history.

The resolved allowance rate is 91.72%, and the average office actions per allowance is 3.17. The rate indicates favorable results among resolved matters, while the action average shows that allowances commonly follow repeated examination interaction rather than an isolated office-action response.

These figures are relevant to applicants with technically dense semiconductor, circuit, or optics claims. The profile suggests experience balancing prosecution volume with continued work on claim distinctions and amendments. Practitioners should treat the allowance rate as an outcome indicator and the action average as a separate planning signal for prosecution effort.

Written from this page's own data; every figure is computed from USPTO records and verified before publication.

Quality Metrics (n=2866 apps, methodology: how we score firms)

91.7%
Allowance Rate
n=2866
+0.41σ
Allowance Rate (norm)
n=2866
3.2
OAs to Allowance
n=2170
-0.04σ
OAs to Allow (norm)
n=2170
1056 days
Time to Allowance
n=2170
+4.8pp
Interview Lift
n=2866
24.7%
RCE Rate
n=2866
1.9%
Appeal Rate
n=2866

Rejection Performance (% of received rejections ultimately overcome)

91.6%
§101 Overcome
n=427
84.4%
§102 Overcome
n=1253
82.5%
§103 Overcome
n=1746
82.0%
§112 Overcome
n=832

Specialization & Scale

H01L, H10W, G06F
Top CPC Subclasses
35%
Top-3 CPC Share
n=2866
1
Practitioners
n=2866
2866.0
Apps / Practitioner
n=2866

Portfolio Summary

79
Total Pending OAs
40
Non-Final OAs
37
Final Rejections
2
Advisory / Quayle

Response Deadline Pressure

Based on the USPTO statutory response window for each pending office action. 23 of the docket's apps have a known mailing date; the rest are excluded from the tile counts.

8
Overdue
2
Due this week
8
Due this month
3
Due in next 60 days
2
Due later

Deadline Fire Line

Every pending office action with a known statutory deadline, placed on a days-until-due axis. Dots left of Today are overdue; the further right, the more runway. Cases that share a deadline window stack vertically. 23 of the docket's apps have a known mailing date.

-30dToday30d60d90d120d
Overdue (8)Due ≤ 7 days (2)Due ≤ 30 days (8)Due ≤ 60 days (3)Due later (2)

Case Difficulty Mix

Difficulty is derived from the rejection statutes on the most recent pending office action. §101-driven and multi-statute cases are graded Hard; §112-only and obviousness-type double-patenting cases are graded Easy; everything else is Medium. "Unknown" means we have not yet parsed a statute for that office action.

26
Hard (33%)
43
Medium (54%)
2
Easy (3%)
8
Unknown (10%)

Rejection Statute Mix

BucketCases
§101 + other3 (4%)
§103 only35 (44%)
§102 only6 (8%)
§112 only2 (3%)
Double-patenting + other2 (3%)
Multi-statute (no §101)23 (29%)
No statute on record8 (10%)

Industry Mix

How the docket's pending cases split across USPTO tech-center bands.

0
Life Sciences
0% of docket
22
Information Tech
28% of docket
0
Communications
0% of docket
55
Semiconductors
70% of docket
1
Mechanical / Eng
1% of docket
1
Business / Other
1% of docket

Time-on-OA Estimate

Manual office-action response work runs about 10 hours per case. The time-saved bands below show what IP Author's prosecution pipeline typically delivers — a conservative 20% on the low end, 35% in the middle, 50% on the high end.

790 h
Manual time on pending OAs
158 h
Time saved (low, 20%)
276 h
Time saved (mid, 35%)
6.9 wks
FTE-weeks freed (mid)

Top Examiners on this docket

ExaminerApps on this docketAllow rateInterview lift
COMBER, KEVIN J 2 82.7% +11.7%
KOLB, THADDEUS J 2 85.7% +20.8%
VALENZUELA, PATRICIA D 2 90.3% +2.0%
BROMELL, ALEXANDRIA Y 1 75.5% +10.3%
RECEK, JASON D 1 70.9% +22.1%
TALUKDAR, ARVIND 1 80.1% +4.3%
WILLIAMS, CLAYTON R 1 81.9% -4.8%
ASSOUMAN, HERVE-LOUIS Y 1 91.4% +4.1%
GEYER, SCOTT B 1 94.2% +4.2%
ANDERSON, WILLIAM H 1 84.9% +18.4%

Quick Wins (7)

Cases in front of an examiner with an allow rate of 80%+ where the difficulty is Easy or Medium. The top 7 ordered by deadline are shown.

App #TitleExaminerDue in
18913807 MICROSERVICE PROVISION AND MANAGEMENT WILLIAMS, CLAYTON R —
18762478 PACKAGE FORMATION METHODS INCLUDING COUPLING A MOLDED ROUTING LAYER TO AN INTEGRATED ROUTING LAYER GEYER, SCOTT B —
18762484 POWER DELIVERY STRUCTURES ANDERSON, WILLIAM H —
18201597 ELECTROSTATIC DISCHARGE PROTECTION CIRCUIT WITH LOW-LEAKAGE FOR LARGE VOLTAGE SWING OF NEGATIVE CURRENT COMBER, KEVIN J —
18201592 ELECTROSTATIC DISCHARGE PROTECTION CIRCUIT WITH LOW-LEAKAGE FOR LARGE VOLTAGE SWING OF POSITIVE CURRENT COMBER, KEVIN J —
17891727 INTEGRATED CONFORMAL THERMAL HEAT SPREADER FOR MULTICHIP COMPOSITE DEVICES VALENZUELA, PATRICIA D —
17855145 MULTIPLE COMPOSITION THERMAL INTERFACE MATERIALS FOR MULTI-DIE PACKAGES VALENZUELA, PATRICIA D —

Hard Cases (26)

Multi-statute / §101-driven matters, or cases in front of an examiner with an allow rate under 30%. The top 8 ordered by deadline are shown.

App #TitleExaminerDue in
17891666 DIE CRACK MITIGATION IN MULTI-CHIP COMPOSITE IC STRUCTURES XU, ZHIJUN 66d overdue
17955235 LOW TEMPERATURE VARACTORS USING VARIABLE CAPACITANCE MATERIALS CHEN, YU 44d overdue
18084438 LOW ALUMINUM CONCENTRATION ALUMINUM GALLIUM NITRIDE INTERLAYER FOR GROUP III-NITRIDE (III-N) DEVICES HANUMASAGAR, SHAMITA S 18d overdue
17891654 IC DIE COMPOSITES WITH INORGANIC INTER-DIE FILL STRUCTURES KOLB, THADDEUS J 10d overdue
17957257 EMBEDDED THIN FILM VARISTOR IN THROUGH GLASS VIAS ANGUIANO, MICHAEL 5d overdue
17903327 METHOD AND APPARATUS TO SELECT ASSIGNABLE DEVICE INTERFACES FOR VIRTUAL DEVICE COMPOSITION KE, PENG 9d
17955187 SELF-ALIGNMENT LAYER WITH LOW-K MATERIAL PROXIMATE TO VIAS GREWAL, HEIM KIRIN 27d
18114120 PROTECTION AGAINST ELECTROMIGRATION WITHIN A LAYER OF AN INTEGRATED CIRCUIT GARCES, NELSON Y 28d

Interview Candidates (7)

Cases in front of an examiner whose interview lift is 10 percentage points or more — i.e. interviewed cases historically resolve more favorably than non-interviewed ones. The top 7 ordered by deadline are shown.

App #TitleExaminerDue in
17891654 IC DIE COMPOSITES WITH INORGANIC INTER-DIE FILL STRUCTURES KOLB, THADDEUS J 10d overdue
17957403 HIGH PERFORMANCE PERMANENT GLASS ARCHITECTURES FOR STACKED INTEGRATED CIRCUIT DEVICES KOLB, THADDEUS J 30d
19372602 Untitled BROMELL, ALEXANDRIA Y —
19260043 TECHNOLOGIES FOR ALLOCATING RESOURCES ACROSS DATA CENTERS RECEK, JASON D —
18762484 POWER DELIVERY STRUCTURES ANDERSON, WILLIAM H —
18201597 ELECTROSTATIC DISCHARGE PROTECTION CIRCUIT WITH LOW-LEAKAGE FOR LARGE VOLTAGE SWING OF NEGATIVE CURRENT COMBER, KEVIN J —
18201592 ELECTROSTATIC DISCHARGE PROTECTION CIRCUIT WITH LOW-LEAKAGE FOR LARGE VOLTAGE SWING OF POSITIVE CURRENT COMBER, KEVIN J —

Client Portfolio (1 client)

Client (Assignee)Pending OAs
Intel 79

Top Art Units

Art UnitApps
281210
28986
28745
28174
28144
28384
28994
24433
28973
28183

Pending Office Actions

App #TitleClientExaminerArt UnitStatutesStatusDue inAIFiled
19372602 Untitled Intel Corporation BROMELL, ALEXANDRIA Y 2156 — Non-Final OA — Pending
19260043 TECHNOLOGIES FOR ALLOCATING RESOURCES ACROSS DATA CENTERS Intel Corporation RECEK, JASON D 2458 §103 Non-Final OA — Pending Jul 03, 2025
18868623 VARIABLE CACHELINE SET MAPPING Intel Corporation TALUKDAR, ARVIND 2132 §102§103 Final Rejection — Pending Nov 22, 2024
18913807 MICROSERVICE PROVISION AND MANAGEMENT Intel Corporation WILLIAMS, CLAYTON R 2443 §103Other Non-Final OA — AI Ready Oct 11, 2024
18907358 ARRAYS OF DOUBLE-SIDED DRAM CELLS INCLUDING CAPACITORS ON THE FRONTSIDE AND BACKSIDE OF A STACKED TRANSISTOR STRUCTURE Intel Corporation ASSOUMAN, HERVE-LOUIS Y 2812 Other Non-Final OA — Pending Oct 04, 2024
18762478 PACKAGE FORMATION METHODS INCLUDING COUPLING A MOLDED ROUTING LAYER TO AN INTEGRATED ROUTING LAYER Intel Corporation GEYER, SCOTT B 2812 §102DP Non-Final OA — Pending Jul 02, 2024
18762484 POWER DELIVERY STRUCTURES Intel Corporation ANDERSON, WILLIAM H 2817 §102Other Non-Final OA — Pending Jul 02, 2024
18734891 VIRTUAL EXECUTION ENVIRONMENT POWER USAGE Intel Corporation KAMRAN, MEHRAN 2196 — Final Rejection — Pending Jun 05, 2024
18668042 MULTI-HEIGHT & MULTI-WIDTH INTERCONNECT LINE METALLIZATION FOR INTEGRATED CIRCUIT STRUCTURES Intel Corporation PATEL, REEMA 2812 §102§103DP Non-Final OA — Pending May 17, 2024
18399494 Comb Laser Source Architectures for Photonic integrated Circuits Intel Corporation PATEL, PREET BAKUL 2874 §103§112 Non-Final OA 71d AI Ready Dec 28, 2023
18399503 SILICON PHOTONIC INTEGRATED CIRCUITS WITH LOCALIZED THICK BURIED INSULATOR Intel Corporation GREEN, TAJANAE NICOLE 2874 §102§103§112 Non-Final OA — Pending Dec 28, 2023
18478589 METHODS, SYSTEMS, APPARATUS, AND ARTICLES OF MANUFACTURE TO MANAGE NETWORK COMMUNICATIONS IN TIME SENSITIVE NETWORKS Intel Corporation WIDHALM DE RODRIG, ANGELA MARIE 2443 §102 Non-Final OA — Pending Sep 29, 2023
18374516 SELF-ALIGNMENT ASSISTED ASSEMBLY ON A STRUCTURAL WAFER FOR HYBRID BONDED DIE STACKS Intel Corporation ONUTA, TIBERIU DAN 2814 — Non-Final OA — Pending Sep 28, 2023
18240271 DEVICE, METHOD AND SYSTEM TO SUPPORT A SYNCHRONOUS DATA FLOW WITH AN IDENTIFICATION OF AN EXECUTABLE TASK Intel Corporation MACKALL, LARRY T 2139 §102 Non-Final OA — Pending Aug 30, 2023
18233199 DEVICE, METHOD AND SYSTEM FOR IN-FIELD LANE TESTING AND REPAIR WITH A THREE-DIMENSIONAL INTEGRATED CIRCUIT Intel Corporation ALEJNIKOV JR, ROBERT P 2857 §102§103 Non-Final OA — Pending Aug 11, 2023
18231695 EXTENDED ERROR MANAGEMENT WITH CONFIGURABLE HEADER LOGS Intel Corporation YU, XINYUAN §101§102§103 Non-Final OA — Pending Aug 08, 2023
18217049 METHODS OF FORMING WAFER LEVEL MULTI-DIE SYSTEM FABRIC INTERCONNECT STRUCTURES Intel Corporation MCCOY, THOMAS WILSON 2814 §102§103 Non-Final OA — Pending Jun 30, 2023
18217056 FORMING POROUS DIELECTRIC STRUCTURES WITH SPATIALLY-CONTROLLED POROSITY Intel Corporation ANYA, IGWE U 2891 §102§103 Non-Final OA — Pending Jun 30, 2023
18216493 PERFORMANCE OPTIMIZATION OF TRANSISTORS SHARING CHANNEL STRUCTURES OF VARYING WIDTH Intel Corporation KIM, TONG-HO 2811 §102§103 Non-Final OA — Pending Jun 29, 2023
18216476 MITIGATION OF THRESHOLD VOLTAGE SHIFT IN BACKSIDE POWER DELIVERY USING BACKSIDE PASSIVATION LAYER Intel Corporation LEE, WOO KYUNG 2815 — Non-Final OA — Pending Jun 29, 2023
18216456 DEVICE, SYSTEM, AND METHOD FOR PROVIDING ISOLATION BETWEEN CORES TO FACILITATE A MULTI-TENANT ENVIRONMENT Intel Corporation CHAN, DANNY 2175 §103 Non-Final OA — Pending Jun 29, 2023
18216485 AND DOUBLE PATTERNING STRATEGY WITH PRINTED ERASABLE DUMMIFICATION Intel Corporation IMTIAZ, S M SOHEL 2812 — Non-Final OA — Pending Jun 29, 2023
18216525 THROUGH GLASS VIAS WITH COMPLIANT LAYER FOR INTEGRATED CIRCUIT DEVICE PACKAGES Intel Corporation LIU, XIAOMING 2812 §102§103 Non-Final OA — Pending Jun 29, 2023
18216447 HIGH-FREQUENCY INTERFACE CIRCUIT PROTECTION FROM ELECTROSTATIC DISCHARGE EVENTS Intel Corporation SREEVATSA, SREEYA 2838 §102§103 Non-Final OA — Pending Jun 29, 2023
18216352 DEVICE, METHOD, AND SYSTEM TO PROVIDE A LIMITED POWER STATES MODE FOR MANAGING PROCESSOR OPERATION Intel Corporation HARRINGTON, CHERI L. 2176 §102§103§112 Non-Final OA — Pending Jun 29, 2023
18216436 HARDWARE-BASED CRYPTOGRAPHIC PROTECTION OF TOKENS Intel Corporation ZARRINEH, SHAHRIAR 2496 §102§103 Non-Final OA — Pending Jun 29, 2023
18343671 METHODS AND APPARATUS TO INCREASE PRIVACY FOR FOLLOW-ME SERVICES Intel Corporation NOAMAN, BASSAM A 2497 — Final Rejection — Pending Jun 28, 2023
18215033 DISTRIBUTED CIRCUIT FOR ELECTROSTATIC DISCHARGE PROTECTION FOR A SIGNAL PAD Intel Corporation JACKSON, STEPHEN W 2838 §102 Non-Final OA — Pending Jun 27, 2023
18331799 METHODS AND APPARATUS TO SLICE NETWORKS FOR WIRELESS SERVICES Intel Corporation HSU, BAILOR CHIA-JONG 2461 §112 Non-Final OA — Pending Jun 08, 2023
18201656 OFFSET VOIDING SCHEME FOR VERTICAL INTERCONNECTS Intel Corporation MINNEY, GABRIEL SEBASTIAN 2897 §103 Non-Final OA — Pending May 24, 2023
18201597 ELECTROSTATIC DISCHARGE PROTECTION CIRCUIT WITH LOW-LEAKAGE FOR LARGE VOLTAGE SWING OF NEGATIVE CURRENT Intel Corporation COMBER, KEVIN J 2838 §103 Non-Final OA — Pending May 24, 2023
18201592 ELECTROSTATIC DISCHARGE PROTECTION CIRCUIT WITH LOW-LEAKAGE FOR LARGE VOLTAGE SWING OF POSITIVE CURRENT Intel Corporation COMBER, KEVIN J 2838 §103Other Non-Final OA — Pending May 24, 2023
18139078 EXECUTION OF CONTAINER IMAGES IN A TRUSTED EXECUTION ENVIRONMENT Intel Corporation COYER, RYAN D 2191 §103 Final Rejection 33d AI Ready Apr 25, 2023
18136972 HARDWARE-BASED ACCELERATORS IN CLOUD NATIVE APPLICATIONS WRITTEN IN HIGH LEVEL PROGRAMMING LANGUAGES Intel Corporation DASCOMB, JACOB D 2198 §103 Final Rejection 21d AI Ready Apr 20, 2023
18133353 OPTICAL FIBER MOUNTS FOR PRINTED CIRCUIT BOARDS AND INTEGRATED CIRCUIT DEVICE PACKAGES Intel Corporation KIANNI, KAVEH C 2874 §102 Non-Final OA — Pending Apr 11, 2023
18296264 DISPLAY SYNCHRONIZATION FOR TIME SENSITIVE NETWORKING Intel Corporation VAUGHN JR, WILLIAM C 2481 — Final Rejection 83d Pending Apr 05, 2023
18129737 METHODS OF FORMING DIE STRUCTURES WITH SCALLOPED SIDEWALLS AND STRUCTURES FORMED THEREBY Intel Corporation STARK, JARRETT J 2898 §103 Final Rejection — Pending Mar 31, 2023
18129690 CO-PACKAGING OF PHOTONIC & ELECTRONIC INTEGRATED CIRCUIT DIE Intel Corporation CHOWDHURY, TARIFUR RASHID 2877 §103 Final Rejection — Pending Mar 31, 2023
18129617 MODULATION OF CHIP PERFORMANCE BY CONTROLLING TRANSISTOR GATE PROFILE Intel Corporation MENZ, DOUGLAS M 2893 §103 Non-Final OA — Pending Mar 31, 2023
18129704 PLASMA ENHANCED ATOMIC LAYER DEPOSITION OF DIELECTRIC MATERIAL UPON OXIDIZABLE MATERIAL Intel Corporation MOVVA, AMAR 2898 §103 Non-Final OA — Pending Mar 31, 2023
18116940 IN-ORDER STREAMING IN-NETWORK COMPUTATION Intel Corporation BARRY, LANCE LEONARD 2443 §103 Final Rejection — Pending Mar 03, 2023
18114120 PROTECTION AGAINST ELECTROMIGRATION WITHIN A LAYER OF AN INTEGRATED CIRCUIT Intel Corporation GARCES, NELSON Y 2814 §102§103 Final Rejection 28d AI Ready Feb 24, 2023
18109774 TECHNOLOGIES FOR COORDINATING DISAGGREGATED ACCELERATOR DEVICE RESOURCES Intel Corporation CAO, DIEM K 2196 §103 Non-Final OA — Pending Feb 14, 2023
18090707 DIE ATTACH IN GLASS CORE PACKAGE THROUGH ORGANIC-TO-ORGANIC BONDING Intel Corporation PALANISWAMY, KRISHNA JAYANTHI 2899 §103§112 Final Rejection — AI Ready Dec 29, 2022
18091270 IC DIE PACKAGES WITH LOW CTE DIELECTRIC MATERIALS Intel Corporation AU, BAC H 2898 §103 Final Rejection 15d AI Ready Dec 29, 2022
18090258 ELECTRO-OPTICAL CIRCUITS WITH LOW-COST SWITCHABLE PHOTONIC INTERFACE Intel Corporation TRAN, HOANG Q 2874 §103 Final Rejection 20d AI Ready Dec 28, 2022
18090140 SOCKET INTERFACE FRAMES FOR DEVICES WITH IMPROVED-PERFORMANCE SUBSTRATES Intel Corporation ARMAND, MARC ANTHONY 2813 §103 Final Rejection — AI Ready Dec 28, 2022
18087517 UNDER BUMP METALLIZATIONS, SOLDER COMPOSITIONS, AND STRUCTURES FOR DIE INTERCONNECTS ON INTEGRATED CIRCUIT PACKAGING Intel Corporation LINDSEY, COLE LEON 2812 §103 Final Rejection 9d overdue AI Ready Dec 22, 2022
18086232 GLASS SUBSTRATE DEVICE WITH THROUGH GLASS CAVITY Intel Corporation JOHNSON, CHRISTOPHER A 2899 §103 Final Rejection — Pending Dec 21, 2022
18084438 LOW ALUMINUM CONCENTRATION ALUMINUM GALLIUM NITRIDE INTERLAYER FOR GROUP III-NITRIDE (III-N) DEVICES Intel Corporation HANUMASAGAR, SHAMITA S 2814 §102§103§112 Final Rejection 18d overdue AI Ready Dec 19, 2022

View all 79 →

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Frequently Asked Questions

What is Essential Patents Group, Llp.'s patent allowance rate?

91.7% of resolved applications prosecuted by Essential Patents Group, Llp. were allowed, across 2,866 applications in USPTO records.

How many office actions does Essential Patents Group, Llp. average before allowance?

3.17 office actions per allowed application on average.

How many pending office actions does Essential Patents Group, Llp. have?

79 pending office actions as of October 2026, for 1 client, before 76 examiners in 39 art units.

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