Prosecution Insights
Last updated: October 25, 2026

Patterson + Sheridan, LLP - Synopsys

Technology areas: Computing & Software • Semiconductors, Circuits & Optics

7 pending office actions • 1 client • 7 examiners • 5 art units • 0 of 7 (0%) have an AI response strategy ready • 34 patents granted in the last 365 days

Analysis

Patterson + Sheridan, LLP - Synopsys has managed 262 career applications, with a technical focus on the Computing & Software area. The firm maintains a resolved allowance rate of 100.0 percent.

The firm reaches allowance with an average of 1.86 office actions per allowance. This average of 1.86 office actions reflects the typical number of interactions required to secure a grant for this client. There are currently 7 pending office actions being handled by the firm.

The combination of 262 career applications and a 100.0 percent allowance rate shows the historical outcome for this portfolio. With 7 pending office actions, the firm continues to actively manage the examination process for new Synopsys filings.

Written from this page's own data; every figure is computed from USPTO records and verified before publication.

Quality Metrics (n=262 apps, methodology: how we score firms)

100.0%
Allowance Rate
n=262
+0.51σ
Allowance Rate (norm)
n=262
1.9
OAs to Allowance
n=147
-0.78σ
OAs to Allow (norm)
n=147
860 days
Time to Allowance
n=147
+0.0pp
Interview Lift
n=262
15.0%
RCE Rate
n=262
1.7%
Appeal Rate
n=262

Rejection Performance (% of received rejections ultimately overcome)

—
§101 Overcome
n=12 (min 20)
90.3%
§102 Overcome
n=72
84.2%
§103 Overcome
n=57
87.0%
§112 Overcome
n=23

Specialization & Scale

G06F, G06N, G11C
Top CPC Subclasses
70%
Top-3 CPC Share
n=262
0
Practitioners
n=262
—
Apps / Practitioner
n=262 (min 20)

Portfolio Summary

7
Total Pending OAs
6
Non-Final OAs
1
Final Rejections
0
Advisory / Quayle

Case Difficulty Mix

Difficulty is derived from the rejection statutes on the most recent pending office action. §101-driven and multi-statute cases are graded Hard; §112-only and obviousness-type double-patenting cases are graded Easy; everything else is Medium. "Unknown" means we have not yet parsed a statute for that office action.

5
Hard (71%)
2
Medium (29%)
0
Easy (0%)
0
Unknown (0%)

Rejection Statute Mix

BucketCases
§101 + other3 (43%)
§103 only2 (29%)
Multi-statute (no §101)2 (29%)

Industry Mix

How the docket's pending cases split across USPTO tech-center bands.

0
Life Sciences
0% of docket
4
Information Tech
57% of docket
0
Communications
0% of docket
3
Semiconductors
43% of docket
0
Mechanical / Eng
0% of docket
0
Business / Other
0% of docket

Time-on-OA Estimate

Manual office-action response work runs about 10 hours per case. The time-saved bands below show what IP Author's prosecution pipeline typically delivers — a conservative 20% on the low end, 35% in the middle, 50% on the high end.

70 h
Manual time on pending OAs
14 h
Time saved (low, 20%)
24 h
Time saved (mid, 35%)
0.6 wks
FTE-weeks freed (mid)

Top Examiners on this docket

ExaminerApps on this docketAllow rateInterview lift
PARIHAR, SUCHIN 1 87.8% +8.9%
ALAWDI, ANWER AHMED 1 75.0% +16.7%
NGUYEN, NHA T 1 87.2% +18.2%
HOUNTON, AWADAGBE GERARD 1 — —
KIM, EUNHEE 1 77.3% +12.2%
OCHOA, JUAN CARLOS 1 67.1% +21.5%
STORK, KYLE R 1 63.2% +28.7%

Quick Wins (1)

Cases in front of an examiner with an allow rate of 80%+ where the difficulty is Easy or Medium. The top 1 ordered by deadline are shown.

App #TitleExaminerDue in
18535934 INCREMENTAL GLITCH ANALYSIS FOR EFFICIENT GLITCH POWER OPTIMIZATION NGUYEN, NHA T —

Hard Cases (5)

Multi-statute / §101-driven matters, or cases in front of an examiner with an allow rate under 30%. The top 5 ordered by deadline are shown.

App #TitleExaminerDue in
18590646 POWER PERFORMANCE AREA OPTIMIZATION IN DESIGN TECHNOLOGY CO-OPTIMIZATION FLOWS PARIHAR, SUCHIN —
18415501 ADAPTIVE AND INCREMENTAL CIRCUIT DESIGN IMPLEMENTATION ALAWDI, ANWER AHMED —
18499021 METRICS FOR INSTANCE RANKING FOR CLASSIFICATION AND REGRESSION HOUNTON, AWADAGBE GERARD —
18141251 ADJUSTMENTS TO SUPERCONDUCTING ELECTRONIC CIRCUIT DESIGNS USING PASSIVE TRANSMISSION LINE MODELING KIM, EUNHEE —
17898088 SUPERVISED MACHINE LEARNING BASED MEMORY AND RUNTIME PREDICTION USING DESIGN AND AUXILIARY CONSTRUCTS STORK, KYLE R —

Interview Candidates (5)

Cases in front of an examiner whose interview lift is 10 percentage points or more — i.e. interviewed cases historically resolve more favorably than non-interviewed ones. The top 5 ordered by deadline are shown.

App #TitleExaminerDue in
18415501 ADAPTIVE AND INCREMENTAL CIRCUIT DESIGN IMPLEMENTATION ALAWDI, ANWER AHMED —
18535934 INCREMENTAL GLITCH ANALYSIS FOR EFFICIENT GLITCH POWER OPTIMIZATION NGUYEN, NHA T —
18141251 ADJUSTMENTS TO SUPERCONDUCTING ELECTRONIC CIRCUIT DESIGNS USING PASSIVE TRANSMISSION LINE MODELING KIM, EUNHEE —
18127376 DYNAMIC CONTROL OF CIRCUIT DESIGN EMULATION OCHOA, JUAN CARLOS —
17898088 SUPERVISED MACHINE LEARNING BASED MEMORY AND RUNTIME PREDICTION USING DESIGN AND AUXILIARY CONSTRUCTS STORK, KYLE R —

Client Portfolio (1 client)

Client (Assignee)Pending OAs
Synopsys, Inc. 7

Top Art Units

Art UnitApps
28513
21261
21881
21861
21281

Pending Office Actions

App #TitleClientExaminerArt UnitStatutesStatusDue inAIFiled
18590646 POWER PERFORMANCE AREA OPTIMIZATION IN DESIGN TECHNOLOGY CO-OPTIMIZATION FLOWS Synopsys, Inc. PARIHAR, SUCHIN 2851 §102§103 Non-Final OA — Pending Feb 28, 2024
18415501 ADAPTIVE AND INCREMENTAL CIRCUIT DESIGN IMPLEMENTATION Synopsys, Inc. ALAWDI, ANWER AHMED 2851 §102§103 Non-Final OA — Pending Jan 17, 2024
18535934 INCREMENTAL GLITCH ANALYSIS FOR EFFICIENT GLITCH POWER OPTIMIZATION Synopsys, Inc. NGUYEN, NHA T 2851 §103 Non-Final OA — Pending Dec 11, 2023
18499021 METRICS FOR INSTANCE RANKING FOR CLASSIFICATION AND REGRESSION Synopsys, Inc. HOUNTON, AWADAGBE GERARD 2126 §101§102§103 Non-Final OA — Pending Oct 31, 2023
18141251 ADJUSTMENTS TO SUPERCONDUCTING ELECTRONIC CIRCUIT DESIGNS USING PASSIVE TRANSMISSION LINE MODELING Synopsys, Inc. KIM, EUNHEE 2188 §101§103§112 Non-Final OA — Pending Apr 28, 2023
18127376 DYNAMIC CONTROL OF CIRCUIT DESIGN EMULATION Synopsys, Inc. OCHOA, JUAN CARLOS 2186 §103 Non-Final OA — Pending Mar 28, 2023
17898088 SUPERVISED MACHINE LEARNING BASED MEMORY AND RUNTIME PREDICTION USING DESIGN AND AUXILIARY CONSTRUCTS Synopsys, Inc. STORK, KYLE R 2128 §101§102§103 Final Rejection — Pending Aug 29, 2022

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Frequently Asked Questions

What is Patterson + Sheridan, LLP - Synopsys's patent allowance rate?

100.0% of resolved applications prosecuted by Patterson + Sheridan, LLP - Synopsys were allowed, across 262 applications in USPTO records.

How many office actions does Patterson + Sheridan, LLP - Synopsys average before allowance?

1.86 office actions per allowed application on average.

How many pending office actions does Patterson + Sheridan, LLP - Synopsys have?

7 pending office actions as of October 2026, for 1 client, before 7 examiners in 5 art units.

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