Technology area: Semiconductors, Circuits & Optics
45 pending office actions • 17 art units • 41 examiners • 0 of 45 (0%) have an AI response strategy ready • 55 patents granted in the last 365 days
Nexperia B.V. has 45 pending office actions in Semiconductors, Circuits & Optics. The portfolio extends across 41 examiners and 17 art units, combining broad examiner exposure with a more concentrated technical structure.
RIVERA-PEREZ, CARLOS O is the busiest examiner, with 2 pending matters. That limited concentration means the portfolio cannot be managed through a single examiner strategy. Art-unit organization can provide a useful first layer for coordinating claim approaches and recurring issues, while examiner-level tracking remains necessary for response practice and prosecution history. The difference between the examiner and art-unit footprints indicates that some technical groupings contain multiple examiner relationships.
Based on the USPTO statutory response window for each pending office action. 12 of the docket's apps have a known mailing date; the rest are excluded from the tile counts.
Every pending office action with a known statutory deadline, placed on a days-until-due axis. Dots left of Today are overdue; the further right, the more runway. Cases that share a deadline window stack vertically. 12 of the docket's apps have a known mailing date.
Difficulty is derived from the rejection statutes on the most recent pending office action. §101-driven and multi-statute cases are graded Hard; §112-only and obviousness-type double-patenting cases are graded Easy; everything else is Medium. "Unknown" means we have not yet parsed a statute for that office action.
| Bucket | Cases |
|---|---|
| §103 only | 15 (33%) |
| §102 only | 5 (11%) |
| §112 only | 3 (7%) |
| Multi-statute (no §101) | 21 (47%) |
| No statute on record | 1 (2%) |
How the docket's pending cases split across USPTO tech-center bands.
Manual office-action response work runs about 10 hours per case. The time-saved bands below show what IP Author's prosecution pipeline typically delivers — a conservative 20% on the low end, 35% in the middle, 50% on the high end.
| Examiner | Apps on this docket | Allow rate | Interview lift |
|---|---|---|---|
| RIVERA-PEREZ, CARLOS O | 2 | 72.2% | +18.8% |
| ZABEL, ANDREW JOHN | 2 | 82.5% | +25.9% |
| CORTES, HOWARD | 2 | 78.5% | +14.5% |
| TRAN, DZUNG | 2 | 83.7% | +5.6% |
| COMBER, KEVIN J | 1 | 82.7% | +11.7% |
| FINCH III, FRED E | 1 | 80.2% | +17.2% |
| EGOAVIL, GUILLERMO J | 1 | 89.8% | +8.5% |
| KNUDSON, BRAD ALLAN | 1 | 84.9% | +18.6% |
| ESKRIDGE, CORY W | 1 | 72.9% | +7.6% |
| WINTERS, SEAN AYERS | 1 | 88.7% | +17.9% |
Cases in front of an examiner with an allow rate of 80%+ where the difficulty is Easy or Medium. The top 3 ordered by deadline are shown.
| App # | Title | Examiner | Due in |
|---|---|---|---|
| 18467786 | REDUCED STRESS CLIP FOR SEMICONDUCTOR DIE | TRAN, DZUNG | 27d |
| 19042180 | MODULE FOR AN ELECTRIC CIRCUIT HAVING A PLANARLY STACKED STRUCTURE FOR POWER PACKAGE TERMINALS, AS WELL AS A RELATED POWER MODULE AND METHOD OF MANUFACTURING SUCH A MODULE | EGOAVIL, GUILLERMO J | — |
| 18897181 | METHOD OF AND INTERMEDIATE FOR MANUFACTURING A SEMICONDUCTOR DIE PACKAGE | KNUDSON, BRAD ALLAN | — |
Multi-statute / §101-driven matters, or cases in front of an examiner with an allow rate under 30%. The top 8 ordered by deadline are shown.
| App # | Title | Examiner | Due in |
|---|---|---|---|
| 18659162 | INDUCTOR-LESS POWER CONVERTER | RIVERA-PEREZ, CARLOS O | 30d overdue |
| 17670893 | SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE | ZABEL, ANDREW JOHN | 2d overdue |
| 17380769 | SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURE | ISAAC, STANETTA D | 20d |
| 18458561 | CARRIER POSITIONING DEVICE | STARK, JARRETT J | 30d |
| 19063430 | THREE PIN CURRENT TRIGGERED TVS PROTECTION SEMICONDUCTOR DEVICE | COMBER, KEVIN J | — |
| 19046608 | SWITCHING STAGE OF A SWITCHED MODE POWER SUPPLY, SMPS, AS WELL AS AN SMPS AND CORRESPONDING METHOD | FINCH III, FRED E | — |
| 18926650 | A SWITCHED MODE POWER SUPPLY ARRANGED FOR EFFICIENTLY POWERING A RANGE OF LOADS AND METHOD OF OPERATING SUCH | RIVERA-PEREZ, CARLOS O | — |
| 18813744 | Semiconductor Device Having an Improved Termination Area Using a Plurality of Laterally Spaced Apart First Regions, as well as a Corresponding Method and Power Device. | WINTERS, SEAN AYERS | — |
Cases in front of an examiner whose interview lift is 10 percentage points or more — i.e. interviewed cases historically resolve more favorably than non-interviewed ones. The top 8 ordered by deadline are shown.
| App # | Title | Examiner | Due in |
|---|---|---|---|
| 18659162 | INDUCTOR-LESS POWER CONVERTER | RIVERA-PEREZ, CARLOS O | 30d overdue |
| 17670893 | SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE | ZABEL, ANDREW JOHN | 2d overdue |
| 19063430 | THREE PIN CURRENT TRIGGERED TVS PROTECTION SEMICONDUCTOR DEVICE | COMBER, KEVIN J | — |
| 19046608 | SWITCHING STAGE OF A SWITCHED MODE POWER SUPPLY, SMPS, AS WELL AS AN SMPS AND CORRESPONDING METHOD | FINCH III, FRED E | — |
| 18926650 | A SWITCHED MODE POWER SUPPLY ARRANGED FOR EFFICIENTLY POWERING A RANGE OF LOADS AND METHOD OF OPERATING SUCH | RIVERA-PEREZ, CARLOS O | — |
| 18897181 | METHOD OF AND INTERMEDIATE FOR MANUFACTURING A SEMICONDUCTOR DIE PACKAGE | KNUDSON, BRAD ALLAN | — |
| 18813744 | Semiconductor Device Having an Improved Termination Area Using a Plurality of Laterally Spaced Apart First Regions, as well as a Corresponding Method and Power Device. | WINTERS, SEAN AYERS | — |
| 18754735 | METHOD OF MANUFACTURING SEMICONDUCTOR ASSEMBLIES | ZABEL, ANDREW JOHN | — |
| Art Unit | Apps |
|---|---|
| 2898 | 7 |
| 2818 | 7 |
| 2838 | 5 |
| 2893 | 5 |
| 2892 | 3 |
| 2812 | 3 |
| 2817 | 2 |
| 2897 | 2 |
| 2899 | 2 |
| 2813 | 2 |
| App # | Title | Examiner | Art Unit | Statutes | Status | Due in | AI | Filed |
|---|---|---|---|---|---|---|---|---|
| 19063430 | THREE PIN CURRENT TRIGGERED TVS PROTECTION SEMICONDUCTOR DEVICE | COMBER, KEVIN J | 2838 | §102§103 | Non-Final OA | — | Pending | Feb 26, 2025 |
| 19046608 | SWITCHING STAGE OF A SWITCHED MODE POWER SUPPLY, SMPS, AS WELL AS AN SMPS AND CORRESPONDING METHOD | FINCH III, FRED E | 2838 | §102§103 | Non-Final OA | — | Pending | Feb 06, 2025 |
| 19042180 | MODULE FOR AN ELECTRIC CIRCUIT HAVING A PLANARLY STACKED STRUCTURE FOR POWER PACKAGE TERMINALS, AS WELL AS A RELATED POWER MODULE AND METHOD OF MANUFACTURING SUCH A MODULE | EGOAVIL, GUILLERMO J | 2847 | §102 | Non-Final OA | — | Pending | Jan 31, 2025 |
| 18926650 | A SWITCHED MODE POWER SUPPLY ARRANGED FOR EFFICIENTLY POWERING A RANGE OF LOADS AND METHOD OF OPERATING SUCH | RIVERA-PEREZ, CARLOS O | 2838 | §102§103 | Non-Final OA | — | Pending | Oct 25, 2024 |
| 18897181 | METHOD OF AND INTERMEDIATE FOR MANUFACTURING A SEMICONDUCTOR DIE PACKAGE | KNUDSON, BRAD ALLAN | 2817 | §103 | Non-Final OA | — | Pending | Sep 26, 2024 |
| 18889581 | CLIP | ESKRIDGE, CORY W | 2898 | §103 | Non-Final OA | — | Pending | Sep 19, 2024 |
| 18813744 | Semiconductor Device Having an Improved Termination Area Using a Plurality of Laterally Spaced Apart First Regions, as well as a Corresponding Method and Power Device. | WINTERS, SEAN AYERS | 2892 | §102§103 | Non-Final OA | — | Pending | Aug 23, 2024 |
| 18791858 | ELECTRONIC DEVICE FOR SHIFTING A VOLTAGE LEVEL | BHATIA, AMIT R | 2842 | §102 | Final Rejection | 9d overdue | Pending | Aug 01, 2024 |
| 18760530 | Overvoltage Protection of Transistor Switches | AMRANY, ADI | 2836 | §112 | Final Rejection | 10d overdue | Pending | Jul 01, 2024 |
| 18754735 | METHOD OF MANUFACTURING SEMICONDUCTOR ASSEMBLIES | ZABEL, ANDREW JOHN | 2818 | §102§103 | Non-Final OA | — | Pending | Jun 26, 2024 |
| 18750213 | SEMICONDUCTOR DIE PACKAGE AND METHOD | LEE, CHEUNG | 2812 | §102§103 | Non-Final OA | — | Pending | Jun 21, 2024 |
| 18678801 | DIE PADDLE | MCCUTCHEON, COLIN RUSSELL | 2892 | §102§103 | Non-Final OA | — | Pending | May 30, 2024 |
| 18666228 | BOND PAD DESIGN FOR SEMICONDUCTOR DEVICE PACKAGES | YECHURI, SITARAMARAO S | 2893 | §103§112 | Non-Final OA | — | Pending | May 16, 2024 |
| 18666265 | SEMICONDUCTOR DEVICE PACKAGE INTERCONNECT AND MANUFACTURING METHOD THEREOF | GEYER, SCOTT B | 2812 | §102 | Non-Final OA | — | Pending | May 16, 2024 |
| 18659162 | INDUCTOR-LESS POWER CONVERTER | RIVERA-PEREZ, CARLOS O | 2838 | §102§103 | Final Rejection | 30d overdue | Pending | May 09, 2024 |
| 18648771 | Forming of Slope Liners in Trench Based Semiconductor Devices | SEDOROOK, DAVID PAUL | 2812 | §102§103 | Non-Final OA | — | Pending | Apr 29, 2024 |
| 18620300 | METHOD FOR MANUFACTURING A SEMICONDUCTOR PACKAGE ASSEMBLY AS WELL AS A SEMICONDUCTOR PACKAGE ASSEMBLY OBTAINED WITH THIS METHOD | HOANG, DZUNG T | 2898 | §103§112 | Non-Final OA | — | Pending | Mar 28, 2024 |
| 18583334 | ELECTRONIC COMPONENT TRANSFER SYSTEM AND METHOD | CORTES, HOWARD | 2818 | §103 | Non-Final OA | — | Pending | Feb 21, 2024 |
| 18583331 | ELECTRONIC COMPONENT TRANSFER SYSTEM AND METHOD | CORTES, HOWARD | 2818 | §103 | Non-Final OA | — | Pending | Feb 21, 2024 |
| 18440017 | DIE PADDLE STANDOFFS IN SEMICONDUCTOR PACKAGES | TRAN, DZUNG | 2893 | §102§103§112 | Non-Final OA | — | Pending | Feb 13, 2024 |
| 18392194 | Nonlinear Gate Vertical Transistor | SHAMSUZZAMAN, MOHAMMED | 2897 | §103 | Final Rejection | — | Pending | Dec 21, 2023 |
| 18540210 | DC-DC Converter with Dynamic MPPT | BEHM, HARRY RAYMOND | 2838 | §103 | Final Rejection | — | Pending | Dec 14, 2023 |
| 18517178 | SEMICONDUCTOR DEVICE | MULERO FLORES, ERIC MANUEL | 2898 | §102§103 | Non-Final OA | — | Pending | Nov 22, 2023 |
| 18514338 | MOSFET GATE FORMATION | CHIU, TSZ K | 2898 | §103 | Non-Final OA | — | Pending | Nov 20, 2023 |
| 18488376 | SEMICONDUCTOR POWER DEVICE WITH IMPROVED JUNCTION TERMINATION EXTENSION | GONZALES, VICENTE ROLANDO | 2899 | §103 | Non-Final OA | — | Pending | Oct 17, 2023 |
| 18482163 | FOUR-LAYER SEMICONDUCTOR DEVICE AND ESD PROTECTION CIRCUIT | NGUYEN, CUONG B | 2818 | §112 | Final Rejection | 22d | Pending | Oct 06, 2023 |
| 18476597 | Method of Improving Package Creepage Distance | JUNG, MICHAEL YOO LIM | 2817 | §102§103Other | Non-Final OA | — | Pending | Sep 28, 2023 |
| 18467786 | REDUCED STRESS CLIP FOR SEMICONDUCTOR DIE | TRAN, DZUNG | 2893 | §103 | Final Rejection | 27d | Pending | Sep 15, 2023 |
| 18467258 | MPS DIODE HAVING NON-UNIFORMLY SPACED WELLS AND METHOD FOR MANUFACTURING THE SAME | SPRENGER, JAIME LYNN | 2893 | Other | Final Rejection | 34d | Pending | Sep 14, 2023 |
| 18241014 | Semiconductor Device and a Method of Manufacturing of a Semiconductor Device | STEPHENSON, KENNETH STEPHEN | 2898 | §102 | Final Rejection | — | Pending | Aug 31, 2023 |
| 18458561 | CARRIER POSITIONING DEVICE | STARK, JARRETT J | 2898 | §103§112 | Final Rejection | 30d | Pending | Aug 30, 2023 |
| 18333854 | METHOD FOR MANUFACTURING A SEMICONDUCTOR PACKAGE ASSEMBLY AS WELL AS SUCH SEMICONDUCTOR PACKAGE ASSEMBLY | SON, ERIKA HEERA | 2893 | §102§103 | Final Rejection | — | Pending | Jun 13, 2023 |
| 18332467 | ELECTRONIC COMPONENT TRANSFER BY LEVITATION | KOCH, GEORGE R | 1745 | §103 | Non-Final OA | — | Pending | Jun 09, 2023 |
| 18329845 | SEMICONDUCTOR PACKAGE ASSEMBLY AND A METHOD OF MANUFACTURING SUCH SEMICONDUCTOR PACKAGE ASSEMBLY | ZARNEKE, DAVID A | 2891 | §103 | Final Rejection | 22d | Pending | Jun 06, 2023 |
| 18329872 | LATERAL ORIENTED METAL-OXIDE-SEMICONDUCTOR, MOS DEVICE COMPRISING A SEMICONDUCTOR BODY | SHOOK, DANIEL P | 2896 | §102§103 | Final Rejection | — | Pending | Jun 06, 2023 |
| 18295977 | APPARATUS FOR TRANSFERRING SEMICONDUCTOR CIRCUITS | TRINH, MINH N | 3729 | §103 | Final Rejection | 21d | Pending | Apr 05, 2023 |
| 18186403 | VERTICAL ORIENTED SEMICONDUCTOR DEVICE HAVING A REDUCED LATERAL FIELD TERMINATION DISTANCE, AS WELL AS A CORRESPONDING METHOD | AHMED, SHAHED | 2813 | §103 | Non-Final OA | — | Pending | Mar 20, 2023 |
| 18153761 | ELECTRONIC PACKAGE AND METHOD FOR MANUFACTURING THE SAME | BULLARD-CONNOR, GENEVIEVE GRACE | 2899 | §103 | Non-Final OA | — | Pending | Jan 12, 2023 |
| 18152845 | SEMICONDUCTOR DEVICE AND ESD PROTECTION DEVICE COMPRISING THE SAME | NICELY, JOSEPH C | 2813 | §112 | Final Rejection | 15d overdue | Pending | Jan 11, 2023 |
| 18147735 | SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE | MARIN, JACOB RAUL | 2818 | §102§103§112 | Non-Final OA | — | Pending | Dec 29, 2022 |
| 18147999 | SEMICONDUCTOR DEVICE AND BIDIRECTIONAL ESD PROTECTION DEVICE COMPRISING THE SAME | FOX, BRANDON C | 2818 | §102 | Non-Final OA | — | Pending | Dec 29, 2022 |
| 18147957 | A MULTI-LAYER SEMICONDUCTOR DEVICE INTERCONNECT INCLUDING INTERWEAVED FINGERS | CUTLER, ETHAN EDWARD | 2892 | §103§112 | Final Rejection | — | Pending | Dec 29, 2022 |
| 18061130 | STEP INTERCONNECT METALLIZATION TO ENABLE PANEL LEVEL PACKAGING | WEGNER, AARON MICHAEL | 2897 | §103 | Non-Final OA | — | Pending | Dec 02, 2022 |
| 17670893 | SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE | ZABEL, ANDREW JOHN | 2818 | §102§103§112 | Final Rejection | 2d overdue | Pending | Feb 14, 2022 |
| 17380769 | SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURE | ISAAC, STANETTA D | 2898 | §102§103 | Final Rejection | 20d | Pending | Jul 20, 2021 |
IP Author helps IP teams respond to office actions faster with AI-generated responses, examiner analytics, and prosecution intelligence.
Start Free TrialNexperia B.V. has 45 pending office actions as of October 2026, spread across 17 art units and 41 examiners.
Carlos O Rivera-Perez has the most, with 2 of Nexperia B.V.'s pending office actions.
Mostly Semiconductors, Circuits & Optics (USPTO Tech Center 2800), based on where its pending office actions are examined.
