Prosecution Insights
Last updated: October 02, 2026

Examiner: LEE, AIDEN Y

Tech Center 2800 • Art Units: 1713 1718 2812

This examiner grants 48% of resolved cases

Analysis

Aiden Y. Lee is an examiner in Art Unit 1713, which is part of Tech Center 2800. He has 492 resolved cases, offering a solid statistical base for evaluating his performance. The allowance rate for this examiner is 47.8 percent, which indicates a more challenging environment for patent applicants. However, the interview lift is 25.3 percent, suggesting that direct engagement with the examiner is a highly effective way to move an application toward allowance. This 25.3 percent lift is a significant incentive for practitioners to schedule interviews.

The median time to allowance is 1286 days, which is a relatively long prosecution cycle of over three and a half years. This 1286-day timeline, combined with the 47.8 percent allowance rate, highlights the difficulties of working in Art Unit 1713. However, the 25.3 percent interview lift provides a clear path to improving those odds. With 492 resolved cases, the data reflects a consistent examination style where communication is key. Practitioners should use the lift to resolve any outstanding issues and potentially shorten the long delays indicated by the 1286-day median pendency. The data from Tech Center 2800 suggests that the interview is a critical tool for success. The 1286-day median pendency remains the primary benchmark for expected prosecution length.

Written from this page's own data; every figure is computed from USPTO records and verified before publication.

Performance Statistics

47.8%
Allow Rate
-20.2% vs TC avg
532
Total Applications
+25.3%
Interview Lift
1286
Avg Prosecution Days
Based on 492 resolved cases, 2023–2026

Rejection Statute Breakdown

0.4%
§101 Eligibility
12.6%
§102 Novelty
50.6%
§103 Obviousness
33.3%
§112 Clarity

Currently Pending Office Actions

App #TitleStatusAssignee
18671496 APPARATUS FOR PROCESSING A SUBSTRATE Non-Final OA Samsung Electronics Co., Ltd.
19265339 MASK ASSEMBLY AND MANUFACTURING METHOD THEREOF Non-Final OA Samsung Display Co., LTD.
18475002 LOADLOCK ASSEMBLY INCLUDING CHILLER UNIT Non-Final OA ASM IP Holding, B.V.
18260841 MANUFACTURING EQUIPMENT FOR LIGHT-EMITTING DEVICE Final Rejection SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
19230170 ORGANIC VAPOR JET PRINTING SYSTEM Non-Final OA The Regents of The University of Michigan
18280374 PLASMA PROCESSING APPARATUS Final Rejection Hitachi High-Tech Corporation
18588597 HYDROPHOBIC TREATMENT DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE Non-Final OA Kioxia Corporation
17799866 HIGH TEMPERATURE SUBSTRATE SUPPORT WITH HEAT SPREADER Non-Final OA LAM RESEARCH CORPORATION
18647384 CHAMBER WALL POLYMER PROTECTION SYSTEM AND METHOD Non-Final OA Taiwan Semiconductor Manufacturing Company, Ltd.
18486291 PROCESS CHAMBER GAS FLOW IMPROVEMENT Final Rejection Applied Materials, Inc.
18222671 SEMICONDUCTOR CHEMICAL PRECURSOR WITH GAS PASSAGES Final Rejection Applied Materials, Inc.
18374679 PLASMA PROCESSING APPARATUS AND SUBSTRATE PROCESSING APPARATUS Final Rejection Tokyo Electron Limited
18369219 SUBSTRATE PROCESSING METHOD, COMPONENT PROCESSING METHOD, AND SUBSTRATE PROCESSING APPARATUS Final Rejection Tokyo Electron Limited
18172785 SUBSTRATE PROCESSING APPARATUS, METHOD OF PROCESSING SUBSTRATE, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, AND RECORDING MEDIUM Final Rejection Kokusai Electric Corporation
18247489 VAPORIZER, GAS SUPPLY APPARATUS, AND METHOD OF CONTROLLING GAS SUPPLY APPARATUS Final Rejection Fujikin Incorporated
18718240 METHOD OF PATTERNING A TARGET LAYER, APPARATUS FOR PATTERNING A TARGET LAYER Non-Final OA ASML NETHERLANDS B.V.

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