Prosecution Insights
Last updated: October 26, 2026

Benjamin T Liu, USPTO Patent Examiner

Listed by the USPTO as LIU, BENJAMIN T

Tech Center 2800 • Art Units: 2812 2893

This examiner grants 75% of resolved cases

Analysis

LIU, BENJAMIN T is a USPTO patent examiner in Tech Center 2800 and Art Unit 2812. The record covers 723 resolved cases, with a 75.1% allowance rate and a median of 1081 days to allowance. The allowance figure indicates that most matters reached allowance, while the median timing shows that prosecution commonly extends beyond the initial examination phase.

The interview lift is 12.4%, reflecting a positive association between interviews and allowance outcomes. The listed companies are Intel, Taiwan Semiconductor Manufacturing, and Samsung Display. The listed firms are Alliance IP, Akona IP, and Alston & Bird. Applicants may treat interviews as a supporting measure while placing primary emphasis on clear written treatment of the relevant limitations.

Written from this page's own data; every figure is computed from USPTO records and verified before publication.

Performance Statistics

75.1%
Allow Rate
+7.1% vs TC avg
763
Total Applications
+12.4%
Interview Lift
1081
Avg Prosecution Days
Based on 723 resolved cases, 2023–2026

Rejection Statute Breakdown

0.4%
§101 Eligibility
31.0%
§102 Novelty
59.2%
§103 Obviousness
9.2%
§112 Clarity

Currently Pending Office Actions

App #TitleStatusAssignee
18515259 METHOD FOR MANUFACTURING SEMICONDUCTOR APPARATUS Final Rejection FUJI ELECTRIC CO., LTD.
18418675 DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME Non-Final OA Samsung Display Co., LTD.
18532692 DISPLAY DEVICE Final Rejection Samsung Display Co., LTD.
18752850 QUANTUM DEVICE AND MANUFACTURING METHOD Non-Final OA NEC Corporation
18686647 Thin Film Transistor, Display Panel and Display Device Non-Final OA BOE TECHNOLOGY GROUP CO., LTD.
18605021 INTERPOSER SUBSTRATE WITH INTEGRATED STEP DIE CAVITY, AND RELATED INTEGRATED CIRCUIT (IC) PACKAGES AND FABRICATION METHODS Non-Final OA QUALCOMM Incorporated
18126833 FOR MEMORY ON PACKAGE WITH REDUCED THICKNESS Non-Final OA Intel Corporation
18089865 INTEGRATED CIRCUIT STRUCTURES HAVING TWO-LEVEL MEMORY Final Rejection Intel Corporation
17823602 THREE-DIMENSIONAL PACKAGE ARCHITECTURE WITH FACE DOWN BRIDGE DIES Non-Final OA Intel Corporation
17871443 MULTI-DIE PANEL-LEVEL HIGH PERFORMANCE COMPUTING COMPONENTS Non-Final OA Intel Corporation
17852039 SINX ADHESION PROMOTER WITH ADHESION HOLE FEATURES IN PACKAGING SUBSTRATE FOR RELIABILITY PERFORMANCE ENHANCEMENT Non-Final OA Intel Corporation
18605034 THERMALLY REGULATED SEMICONDUCTOR DEVICE Non-Final OA Micron Technology, Inc.
18820533 SEMICONDUCTOR MEMORY DEVICE Non-Final OA Kioxia Corporation
18668478 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE Non-Final OA Kioxia Corporation
18584933 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SEMICONDUCTOR DEVICE Non-Final OA SK hynix Inc.
18509052 GAN-BASED, LATERAL-CONDUCTION, ELECTRONIC DEVICE WITH IMPROVED METALLIC LAYERS LAYOUT Non-Final OA STMICROELECTRONICS S.R.L.
18731031 SEMICONDUCTOR DEVICE AND METHOD OF FORMING THEREOF Non-Final OA TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
18433509 TRAPPING FILM FOR DEEP TRENCH ISOLATION STRUCTURE Non-Final OA Taiwan Semiconductor Manufacturing Company, Ltd.
18521913 FIN FIELD EFFECT TRANSISTOR (FINFET) DEVICE STRUCTURE Final Rejection TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
18760800 EPITAXY REGIONS WITH LARGE LANDING AREAS FOR CONTACT PLUGS Non-Final OA Taiwan Semiconductor Manufacturing Co., Ltd.
18374410 POWER MODULE Final Rejection UT-Battelle, LLC

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Frequently Asked Questions

What is examiner Benjamin T Liu's allowance rate?

75.1% of resolved applications examined by Benjamin T Liu were allowed (723 resolved cases), compared with 82.1% across Art Unit 2812 over the last five years.

Does an interview help with examiner Benjamin T Liu?

This examiner's interview lift is +12.4 percentage points: the difference in allowance rate between resolved applications that had an examiner interview and those that did not.

How long does examiner Benjamin T Liu take to allow a patent?

Applications allowed by Benjamin T Liu took 1,081 days on average from filing to allowance.

Which art unit does examiner Benjamin T Liu work in?

Benjamin T Liu examines applications in Art Unit 2812 in Tech Center 2800 (Semiconductors, Circuits & Optics).

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