Technology areas: Computing & Software • Semiconductors, Circuits & Optics
101 pending office actions • 59 art units • 95 examiners • 0 of 101 (0%) have an AI response strategy ready • 217 patents granted in the last 365 days
Amd has 97 pending office actions in Computing & Software. The portfolio spans 91 distinct examiners and 60 distinct art units, combining a substantial workload with broad distribution across examination channels. Repeated assignments at both levels create opportunities for issue tracking, but the number of technical contexts requires disciplined matter-level review.
LEE, ERIC D is the busiest examiner, with 2 pending matters. Those matters may be reviewed together for recurring claim or prior-art themes, while the larger portfolio demands centralized deadline management and consistent software terminology. Examiner-specific arguments remain important because the assignments are widely dispersed.
Based on the USPTO statutory response window for each pending office action. 35 of the docket's apps have a known mailing date; the rest are excluded from the tile counts.
Every pending office action with a known statutory deadline, placed on a days-until-due axis. Dots left of Today are overdue; the further right, the more runway. Cases that share a deadline window stack vertically. 35 of the docket's apps have a known mailing date.
Difficulty is derived from the rejection statutes on the most recent pending office action. §101-driven and multi-statute cases are graded Hard; §112-only and obviousness-type double-patenting cases are graded Easy; everything else is Medium. "Unknown" means we have not yet parsed a statute for that office action.
| Bucket | Cases |
|---|---|
| §101 only | 1 (1%) |
| §101 + other | 8 (8%) |
| §103 only | 41 (41%) |
| §102 only | 7 (7%) |
| §112 only | 5 (5%) |
| Double-patenting + other | 2 (2%) |
| Multi-statute (no §101) | 37 (37%) |
How the docket's pending cases split across USPTO tech-center bands.
Manual office-action response work runs about 10 hours per case. The time-saved bands below show what IP Author's prosecution pipeline typically delivers — a conservative 20% on the low end, 35% in the middle, 50% on the high end.
| Examiner | Apps on this docket | Allow rate | Interview lift |
|---|---|---|---|
| LEE, ERIC D | 2 | 81.5% | +19.3% |
| DUONG, HUY | 2 | 69.7% | +28.5% |
| PRIFTI, AUREL | 2 | 82.9% | +22.1% |
| CLEARY, THOMAS J | 2 | 72.8% | +15.7% |
| SADLER, NATHAN | 2 | 70.9% | +26.4% |
| RIGGINS, ARI FAITH COLEMA | 2 | 55.6% | +55.0% |
| CHAPPELL, DANIEL C | 1 | 80.8% | +45.4% |
| LAUTURE, JOSEPH J | 1 | 95.0% | +0.9% |
| WONG, TITUS | 1 | 77.5% | +19.6% |
| MAI, LAM T | 1 | 96.1% | +1.1% |
Cases in front of an examiner with an allow rate of 80%+ where the difficulty is Easy or Medium. The top 7 ordered by deadline are shown.
| App # | Title | Examiner | Due in |
|---|---|---|---|
| 19232658 | LOCALIZED AND RELOCATABLE SOFTWARE PLACEMENT AND NOC-BASED ACCESS TO MEMORY CONTROLLERS | CHAPPELL, DANIEL C | — |
| 19015963 | DYNAMIC DATA CONVERSION FOR NETWORK COMPUTER SYSTEMS | LAUTURE, JOSEPH J | — |
| 18999290 | ADAPTIVE QUANTIZATION AND COMPRESSION FOR VARIABLE-LENGTH COLLECTIVE COMMUNICATION | MAI, LAM T | — |
| 18589398 | MODULAR INTERCONNECT FOR AN INTEGRATED CIRCUIT DEVICE | LEE, ERIC D | — |
| 18139659 | PREDICTION OF ROUTING CONGESTION | LEE, ERIC D | — |
| 19082412 | EARLY DISPLAY ACTIVATION USING BUFFER MEMORY OF ACCELERATED PROCESSOR | PRIFTI, AUREL | — |
| 18476082 | DEVICES, SYSTEMS, AND METHODS FOR DYNAMICALLY CHANGING FREQUENCIES OF CLOCKS FOR THE DATA LINK LAYER WITHOUT DOWNTIME | PRIFTI, AUREL | — |
Multi-statute / §101-driven matters, or cases in front of an examiner with an allow rate under 30%. The top 8 ordered by deadline are shown.
| App # | Title | Examiner | Due in |
|---|---|---|---|
| 19040546 | HUE-ADAPTIVE SATURATION INCREASE FOR OLED DISPLAY POWER REDUCTION | PIZIALI, JEFFREY J | 88d overdue |
| 18620732 | SOURCE BASED LOCAL DIMMING | BOCAR, DONNA V | 15d overdue |
| 18478757 | CACHE VIRTUALIZATION | SADLER, NATHAN | 11d overdue |
| 17894873 | FRACTIONAL LOGARITHMIC NUMBER SYSTEM ADDER | BUI, KENNY KIM | 3d overdue |
| 18215685 | HIGH-BANDWIDTH THREE-DIMENSIONAL (3D) DIE STACK | BRASFIELD, QUINTON A | 7d |
| 18189995 | REDUCING VOLTAGE DROOP BY LIMITING ASSIGNMENT OF WORK BLOCKS TO COMPUTE CIRCUITS | ZHAO, BING | 14d |
| 18394668 | AN AREA AND POWER EFFICIENT CLOCK DATA RECOVERY (CDR) AND ADAPTATION IMPLEMENTATION FOR DENSE WAVELENGTH-DIVISION MULTIPLEXING (DWDM) OPTICAL LINKS | BAIG, ADNAN | 28d |
| 18622680 | SYSTEMS AND METHODS FOR DATA TRANSFER CONTROL CIRCUITRY | LEWIS-TAYLOR, DAYTON A. | 29d |
Cases in front of an examiner whose interview lift is 10 percentage points or more — i.e. interviewed cases historically resolve more favorably than non-interviewed ones. The top 8 ordered by deadline are shown.
| App # | Title | Examiner | Due in |
|---|---|---|---|
| 18346070 | Mitigation Of Undershoot And Overshoot On A Power Rail | CLEARY, THOMAS J | 22d overdue |
| 18478757 | CACHE VIRTUALIZATION | SADLER, NATHAN | 11d overdue |
| 19232658 | LOCALIZED AND RELOCATABLE SOFTWARE PLACEMENT AND NOC-BASED ACCESS TO MEMORY CONTROLLERS | CHAPPELL, DANIEL C | — |
| 19006047 | PROTOCOL ENHANCEMENTS FOR LOW LATENCY APPLICATIONS | WONG, TITUS | — |
| 18589398 | MODULAR INTERCONNECT FOR AN INTEGRATED CIRCUIT DEVICE | LEE, ERIC D | — |
| 18139659 | PREDICTION OF ROUTING CONGESTION | LEE, ERIC D | — |
| 18065491 | SYNTHESIS FOR MATRIX MULTIPLICATION USING A DATA PROCESSING ARRAY | DUONG, HUY | — |
| 17975879 | REDUCTION TREE HAVING INTERMEDIATE QUANTIZATION BETWEEN REDUCTION OPERATORS | DUONG, HUY | — |
| Art Unit | Apps |
|---|---|
| 2851 | 7 |
| 2175 | 5 |
| 2197 | 4 |
| 2176 | 4 |
| 2139 | 3 |
| 2845 | 3 |
| 2124 | 3 |
| 2196 | 3 |
| 2182 | 3 |
| 3715 | 3 |
| App # | Title | Examiner | Art Unit | Statutes | Status | Due in | AI | Filed |
|---|---|---|---|---|---|---|---|---|
| 19232658 | LOCALIZED AND RELOCATABLE SOFTWARE PLACEMENT AND NOC-BASED ACCESS TO MEMORY CONTROLLERS | CHAPPELL, DANIEL C | 2139 | §103DP | Non-Final OA | — | Pending | Jun 09, 2025 |
| 19015963 | DYNAMIC DATA CONVERSION FOR NETWORK COMPUTER SYSTEMS | LAUTURE, JOSEPH J | 2845 | §112 | Non-Final OA | — | Pending | Jan 10, 2025 |
| 19006047 | PROTOCOL ENHANCEMENTS FOR LOW LATENCY APPLICATIONS | WONG, TITUS | 2181 | §112 | Non-Final OA | — | Pending | Dec 30, 2024 |
| 18999290 | ADAPTIVE QUANTIZATION AND COMPRESSION FOR VARIABLE-LENGTH COLLECTIVE COMMUNICATION | MAI, LAM T | 2845 | §112 | Non-Final OA | — | Pending | Dec 23, 2024 |
| 18898370 | OFFLOADING OPERATIONS USING A NETWORK INTERFACE CONTROLLER | CHERY, MARDOCHEE | 2133 | §102§103 | Non-Final OA | — | Pending | Sep 26, 2024 |
| 18895644 | COMMUNICATION OPTIMIZATION FOR MoE BY OFFLOADING EXPERTS TO NICs | DO, CHAT C | 2193 | §103 | Non-Final OA | — | Pending | Sep 25, 2024 |
| 18807703 | IIC WITH ADAPTIVE CHIP-TO-CHIP INTERFACE TO SUPPORT DIFFERENT CHIP-TO-CHIP PROTOCOLS | PHAN, RAYMOND NGAN | 2175 | §102Other | Final Rejection | 4d overdue | Pending | Aug 16, 2024 |
| 18758280 | DYNAMICALLY POOLED ALLOCATIONS OF MEMORY BUFFERS ON SPATIAL COMPUTE ARCHITECTURES | MACASIANO, JOANNE GONZALES | 2197 | §102§103Other | Non-Final OA | — | Pending | Jun 28, 2024 |
| 18759722 | TRANSMISSION AND PROCESSING OF DATA IN PARALLEL SYSTEMS | JACOB, AJITH | 2161 | §103 | Non-Final OA | 13d | Pending | Jun 28, 2024 |
| 18758300 | DYNAMIC ALLOCATION OF WORK AND DATA ON SPATIAL COMPUTE ARCHITECTURES | WOOD, WILLIAM C | 2193 | §103 | Non-Final OA | — | Pending | Jun 28, 2024 |
| 18759671 | TRANSMISSION AND PROCESSING OF DATA IN PARALLEL SYSTEMS | NILSSON, ERIC | 2122 | §102§103 | Non-Final OA | — | Pending | Jun 28, 2024 |
| 18731006 | UNALIGNED LOAD AND STORE IN A CORE | VICARY, KEITH E | 2183 | §103§112 | Final Rejection | — | Pending | May 31, 2024 |
| 18658906 | EDGE COUPLER BEAM DEFLECTION SYSTEM | SMITH, CHAD | 2874 | §102§103 | Final Rejection | — | Pending | May 08, 2024 |
| 18589398 | MODULAR INTERCONNECT FOR AN INTEGRATED CIRCUIT DEVICE | LEE, ERIC D | 2851 | §102 | Non-Final OA | — | Pending | Feb 27, 2024 |
| 18443243 | MULTI-WAVELENGTH POLARIZATION DIVERSIFIED OPTICAL RECEIVER CONFIGURATION | CONNELLY, MICHELLE R | 2874 | §102§103 | Non-Final OA | — | Pending | Feb 15, 2024 |
| 18394668 | AN AREA AND POWER EFFICIENT CLOCK DATA RECOVERY (CDR) AND ADAPTATION IMPLEMENTATION FOR DENSE WAVELENGTH-DIVISION MULTIPLEXING (DWDM) OPTICAL LINKS | BAIG, ADNAN | 2461 | §103§112 | Final Rejection | 28d | Pending | Dec 22, 2023 |
| 18389974 | REDUCTION OF STUCK CHANNELS AT A NEURAL NETWORK | WOOLWINE, SHANE D | 2124 | §102§103 | Non-Final OA | — | Pending | Dec 20, 2023 |
| 18535491 | FINE-TUNING OF NEURAL NETWORKS | RYLANDER, BART I | 2124 | §103 | Non-Final OA | — | Pending | Dec 11, 2023 |
| 18526364 | SUBSTRATE NOISE ISOLATION STRUCTURES FOR ELECTRONIC DEVICES | MILLER, ALEXANDER MICHAEL | 2898 | §102§103§112 | Non-Final OA | — | Pending | Dec 01, 2023 |
| 18501868 | SYSTEMS AND METHODS FOR TASK MANAGEMENT | KIM, SISLEY NAHYUN | 2196 | §103 | Final Rejection | 1d overdue | Pending | Nov 03, 2023 |
| 18384302 | APPARATUS AND METHOD OF PRINTING SOLDER ON PRINTED CIRCUIT BOARD FOR WARPAGE COMPENSATION | LEGASPI, EUGENE REY DEVERA | 3729 | §103§112 | Non-Final OA | — | Pending | Oct 26, 2023 |
| 18381052 | EFFICIENT METHOD FOR THE LATCH TIMING ANALYSIS OF ELECTRONIC DESIGNS | GARBOWSKI, LEIGH M | 2851 | §103§112 | Non-Final OA | — | Pending | Oct 17, 2023 |
| 18371937 | CO-SIMULATION ON A SYSTEM-ON-CHIP | GEBRESILASSIE, KIBROM K | 2189 | §102§103 | Non-Final OA | — | Pending | Sep 22, 2023 |
| 18242246 | RANDOMIZATION OF INSTRUCTION EXECUTION FLOW FOR GLITCH PROTECTION | CHEN, ZHI | 2196 | §103 | Non-Final OA | — | Pending | Sep 05, 2023 |
| 18241140 | STIFFENER WITH INTEGRATED CONNECTORS | RAMOS-DIAZ, FERNANDO JOSE | 2818 | §103 | Final Rejection | 1d overdue | Pending | Aug 31, 2023 |
| 18226193 | SYSTEM-ON-CHIP HAVING MULTIPLE CIRCUITS AND MEMORY CONTROLLER IN SEPARATE AND INDEPENDENT POWER DOMAINS | AYASH, MARWAN | 2133 | §103§112 | Non-Final OA | — | Pending | Jul 25, 2023 |
| 18215685 | HIGH-BANDWIDTH THREE-DIMENSIONAL (3D) DIE STACK | BRASFIELD, QUINTON A | 2814 | §102§103 | Non-Final OA | 7d | Pending | Jun 28, 2023 |
| 18214381 | BUILDING MULTI-DIE FPGAS USING CHIP-ON-WAFER TECHNOLOGY | PIZARRO CRESPO, MARCOS D | 2814 | §102§103§112 | Final Rejection | — | Pending | Jun 26, 2023 |
| 18211465 | SYNTHESIS OF SIMULATION-DIRECTED STATEMENTS | KIK, PHALLAKA | 2851 | §103 | Non-Final OA | — | Pending | Jun 19, 2023 |
| 18204658 | SELF-AUTHENTICATION OF DATA STORED OFF-CHIP | LANIER, BENJAMIN E | 2437 | §103 | Final Rejection | 12d | Pending | Jun 01, 2023 |
| 18139659 | PREDICTION OF ROUTING CONGESTION | LEE, ERIC D | 2851 | §103 | Final Rejection | — | Pending | Apr 26, 2023 |
| 18065491 | SYNTHESIS FOR MATRIX MULTIPLICATION USING A DATA PROCESSING ARRAY | DUONG, HUY | 2182 | §101§102§103 | Non-Final OA | — | Pending | Dec 13, 2022 |
| 17975879 | REDUCTION TREE HAVING INTERMEDIATE QUANTIZATION BETWEEN REDUCTION OPERATORS | DUONG, HUY | 2182 | §102§103§112 | Non-Final OA | — | Pending | Oct 28, 2022 |
| 17894873 | FRACTIONAL LOGARITHMIC NUMBER SYSTEM ADDER | BUI, KENNY KIM | 2182 | §101§103§112 | Non-Final OA | 3d overdue | Pending | Aug 24, 2022 |
| 17892852 | SOFTMAX AND LOG SOFTMAX METHOD AND SYSTEM | OCHOA, JUAN CARLOS | 2186 | §101 | Non-Final OA | — | Pending | Aug 22, 2022 |
| 17867625 | ADAPTIVE MATRIX MULTIPLIERS | SANDIFER, MATTHEW D | 2151 | §112 | Non-Final OA | 55d | Pending | Jul 18, 2022 |
| 19093097 | AUTOMATED DATA-DRIVEN SYSTEM TO OPTIMIZE OVERCLOCKING | ABBASZADEH, JAWEED A | 2176 | §102§103Other | Non-Final OA | — | Pending | Mar 27, 2025 |
| 19082412 | EARLY DISPLAY ACTIVATION USING BUFFER MEMORY OF ACCELERATED PROCESSOR | PRIFTI, AUREL | 2175 | §103 | Non-Final OA | — | Pending | Mar 18, 2025 |
| 19040546 | HUE-ADAPTIVE SATURATION INCREASE FOR OLED DISPLAY POWER REDUCTION | PIZIALI, JEFFREY J | 2628 | §103§112 | Non-Final OA | 88d overdue | Pending | Jan 29, 2025 |
| 19007218 | DYNAMIC VOLTAGE MARGIN ADJUSTMENT BASED ON WORKLOAD CHARACTERISTICS | CLEARY, THOMAS J | 2175 | §102§103§112 | Non-Final OA | — | Pending | Dec 31, 2024 |
| 18930687 | TRACING AI GENERATED CODE | SHOUSHA, CHRISTIANE | 2199 | §101§103§112 | Non-Final OA | — | Pending | Oct 29, 2024 |
| 18898851 | MULTI-HOST REMOTE MEMORY ACCESS | MA, WEI | 2135 | §103§112 | Non-Final OA | — | Pending | Sep 27, 2024 |
| 18896418 | METHODS AND SYSTEMS FOR SYNCHRONIZING TRUSTED OPERATING SYSTEMS | CARNES, THOMAS A | 2436 | §103 | Final Rejection | — | Pending | Sep 25, 2024 |
| 18758751 | MEMORY DAMAGE DETECTION DURING INTEGRATED CIRCUIT DEVICE BOOT | PRETLOW, DEMETRIUS R | 2858 | §103 | Non-Final OA | — | Pending | Jun 28, 2024 |
| 18745763 | GAME INTERFACE CLASSIFICATION USING ML AND DRIVER OPTIMIZATION | MOSSER, ROBERT E | 3715 | §101§102 | Final Rejection | — | Pending | Jun 17, 2024 |
| 18680368 | CHIPLET CLOCK FORWARDING ARCHITECTURE | NGUYEN, PHIL K | 2176 | §103 | Non-Final OA | — | Pending | May 31, 2024 |
| 18622770 | SYSTEMS AND METHODS FOR GRAPHICS PROCESSING UNITS WITH ENHANCED RESOURCE BARRIERS | KAZIMI, HANI M | 3691 | §102 | Non-Final OA | — | Pending | Mar 29, 2024 |
| 18621676 | FIRMWARE PARTITIONING FOR EFFICIENT WORLD SWITCH | NGO, THANH | 2198 | §103§112 | Non-Final OA | — | Pending | Mar 29, 2024 |
| 18621499 | CACHE ARCHITECTURE HAVING VARIABLY-SIZED CACHE LINES | RUTZ, JARED IAN | 2135 | §103 | Non-Final OA | — | Pending | Mar 29, 2024 |
| 18622725 | SYSTEMS AND METHODS FOR PERFORMING DATA COMMUNICATIONS OVER A DATA COMMUNICATIONS BUS | PATEL, PARTHKUMAR | 2479 | §103 | Non-Final OA | 35d | Pending | Mar 29, 2024 |
IP Author helps IP teams respond to office actions faster with AI-generated responses, examiner analytics, and prosecution intelligence.
Start Free TrialAmd has 101 pending office actions as of October 2026, spread across 59 art units and 95 examiners.
Eric D Lee has the most, with 2 of Amd's pending office actions.
Mostly Computing & Software (USPTO Tech Center 2100), based on where its pending office actions are examined.
