Prosecution Insights
Prosecution Insights
Technology areas: Computing & Software • Semiconductors, Circuits & Optics
5 pending office actions • 2 clients • 5 examiners • 5 art units • 0 of 5 (0%) have an AI response strategy ready
Artie Pennington Law Offices, PLLC has managed 100 career applications, primarily in the Semiconductors, Circuits & Optics technology area. The firm achieves a resolved allowance rate of 96.05 percent. Currently, there are 4 pending office actions under management.
The firm averages 2.88 office actions per allowance. This average of 2.88 serves as a benchmark for practitioners to estimate the typical duration of the prosecution process. The 100 career applications demonstrate the firm's experience. The 4 pending office actions show the current workload. The 96.05 percent allowance rate underscores the firm's performance in the Semiconductors, Circuits & Optics sector. Practitioners can use these metrics to plan for future filings.
Based on the USPTO statutory response window for each pending office action. 3 of the docket's apps have a known mailing date; the rest are excluded from the tile counts.
Every pending office action with a known statutory deadline, placed on a days-until-due axis. Dots left of Today are overdue; the further right, the more runway. Cases that share a deadline window stack vertically. 3 of the docket's apps have a known mailing date.
Difficulty is derived from the rejection statutes on the most recent pending office action. §101-driven and multi-statute cases are graded Hard; §112-only and obviousness-type double-patenting cases are graded Easy; everything else is Medium. "Unknown" means we have not yet parsed a statute for that office action.
| Bucket | Cases |
|---|---|
| §103 only | 1 (20%) |
| Multi-statute (no §101) | 4 (80%) |
How the docket's pending cases split across USPTO tech-center bands.
Manual office-action response work runs about 10 hours per case. The time-saved bands below show what IP Author's prosecution pipeline typically delivers — a conservative 20% on the low end, 35% in the middle, 50% on the high end.
| Examiner | Apps on this docket | Allow rate | Interview lift |
|---|---|---|---|
| ALLI, KASIM A | 1 | 65.8% | +36.4% |
| THOMAS, ERIC W | 1 | 82.5% | -1.9% |
| LIU, XIAOMING | 1 | 86.5% | +10.7% |
| LOHAKARE, PRATIKSHA JAYANT | 1 | 82.3% | +15.3% |
| VARGHESE, ROSHN K | 1 | 67.5% | +20.6% |
Cases in front of an examiner with an allow rate of 80%+ where the difficulty is Easy or Medium. The top 1 ordered by deadline are shown.
| App # | Title | Examiner | Due in |
|---|---|---|---|
| 18206933 | Inductors Embedded in Package Substrate and Board and Method and System for Manufacturing the Same | LOHAKARE, PRATIKSHA JAYANT | 14d |
Multi-statute / §101-driven matters, or cases in front of an examiner with an allow rate under 30%. The top 4 ordered by deadline are shown.
| App # | Title | Examiner | Due in |
|---|---|---|---|
| 18378235 | Method and Apparatus for Prevention, Cessation, Detection, and Monitoring of Cracks in Substrates | LIU, XIAOMING | 30d overdue |
| 18429374 | Low-Equivalent-Series-Resistance Capacitors with Solid-State Current Collectors Using Conductive Inks | THOMAS, ERIC W | 76d |
| 18796021 | Apparatus and Method for Implementing a Loop Prediction of Multiple Basic Blocks | ALLI, KASIM A | — |
| 18138050 | Through Package Vertical Interconnect and Method of Making Same | VARGHESE, ROSHN K | — |
Cases in front of an examiner whose interview lift is 10 percentage points or more — i.e. interviewed cases historically resolve more favorably than non-interviewed ones. The top 4 ordered by deadline are shown.
| App # | Title | Examiner | Due in |
|---|---|---|---|
| 18378235 | Method and Apparatus for Prevention, Cessation, Detection, and Monitoring of Cracks in Substrates | LIU, XIAOMING | 30d overdue |
| 18206933 | Inductors Embedded in Package Substrate and Board and Method and System for Manufacturing the Same | LOHAKARE, PRATIKSHA JAYANT | 14d |
| 18796021 | Apparatus and Method for Implementing a Loop Prediction of Multiple Basic Blocks | ALLI, KASIM A | — |
| 18138050 | Through Package Vertical Interconnect and Method of Making Same | VARGHESE, ROSHN K | — |
| Client (Assignee) | Pending OAs |
|---|---|
| Chipletz | 4 |
| Condor Computing Corporation | 1 |
| Art Unit | Apps |
|---|---|
| 2183 | 1 |
| 2847 | 1 |
| 2812 | 1 |
| 2818 | 1 |
| 2896 | 1 |
| App # | Title | Client | Examiner | Art Unit | Statutes | Status | Due in | AI | Filed |
|---|---|---|---|---|---|---|---|---|---|
| 18796021 | Apparatus and Method for Implementing a Loop Prediction of Multiple Basic Blocks | Condor Computing Corporation | ALLI, KASIM A | 2183 | §103§112 | Final Rejection | — | Pending | Aug 06, 2024 |
| 18429374 | Low-Equivalent-Series-Resistance Capacitors with Solid-State Current Collectors Using Conductive Inks | Chipletz, Inc. | THOMAS, ERIC W | 2847 | §102§103§112 | Final Rejection | 76d | Pending | Jan 31, 2024 |
| 18378235 | Method and Apparatus for Prevention, Cessation, Detection, and Monitoring of Cracks in Substrates | Chipletz, Inc. | LIU, XIAOMING | 2812 | §102§103 | Final Rejection | 30d overdue | Pending | Oct 10, 2023 |
| 18206933 | Inductors Embedded in Package Substrate and Board and Method and System for Manufacturing the Same | Chipletz, Inc. | LOHAKARE, PRATIKSHA JAYANT | 2818 | §103 | Final Rejection | 14d | Pending | Jun 07, 2023 |
| 18138050 | Through Package Vertical Interconnect and Method of Making Same | Chipletz, Inc. | VARGHESE, ROSHN K | 2896 | §102§103§112 | Non-Final OA | — | Pending | Apr 22, 2023 |
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