Prosecution Insights
Prosecution Insights
Technology area: Computing & Software
6 pending office actions • 1 client • 6 examiners • 1 art unit • 0 of 6 (0%) have an AI response strategy ready • 31 patents granted in the last 365 days
Patterson + Sheridan, LLP - Synopsys manages 262 career applications in Computing & Software. The firm has a resolved allowance rate of 100.0 percent. Prosecution averages 1.8 office actions per allowance. Currently, there are 2 pending office actions.
This number of active cases follows a history of 262 career applications. The 100.0 percent resolved allowance rate demonstrates the firm's success in the Computing & Software sector. The 1.8 average office actions per allowance suggests a strategy for resolving examiner issues. This firm's data shows a combination of its success rate and efficiency. The 100.0 percent resolved allowance rate is a metric for its 262 career applications. With 2 pending office actions, the firm's current workload is a specific part of its history, yet it maintains a track record of securing grants with an average of 1.8 office actions. The 1.8 average office actions per allowance is a defining characteristic of its prosecution.
Difficulty is derived from the rejection statutes on the most recent pending office action. §101-driven and multi-statute cases are graded Hard; §112-only and obviousness-type double-patenting cases are graded Easy; everything else is Medium. "Unknown" means we have not yet parsed a statute for that office action.
| Bucket | Cases |
|---|---|
| §101 + other | 2 (33%) |
| §103 only | 1 (17%) |
| §112 only | 1 (17%) |
| Multi-statute (no §101) | 2 (33%) |
How the docket's pending cases split across USPTO tech-center bands.
Manual office-action response work runs about 10 hours per case. The time-saved bands below show what IP Author's prosecution pipeline typically delivers — a conservative 20% on the low end, 35% in the middle, 50% on the high end.
| Examiner | Apps on this docket | Allow rate | Interview lift |
|---|---|---|---|
| PARIHAR, SUCHIN | 1 | 87.8% | +8.9% |
| ALAWDI, ANWER AHMED | 1 | 75.0% | +16.7% |
| AISAKA, BRYCE M | 1 | 87.4% | +10.5% |
| HOUNTON, AWADAGBE GERARD | 1 | — | — |
| KIM, EUNHEE | 1 | 77.4% | +12.0% |
| OCHOA, JUAN CARLOS | 1 | 67.3% | +22.1% |
Cases in front of an examiner with an allow rate of 80%+ where the difficulty is Easy or Medium. The top 1 ordered by deadline are shown.
| App # | Title | Examiner | Due in |
|---|---|---|---|
| 18560283 | METAL-INSULATOR-METAL CAPACITOR INSERTION | AISAKA, BRYCE M | — |
Multi-statute / §101-driven matters, or cases in front of an examiner with an allow rate under 30%. The top 4 ordered by deadline are shown.
| App # | Title | Examiner | Due in |
|---|---|---|---|
| 18590646 | POWER PERFORMANCE AREA OPTIMIZATION IN DESIGN TECHNOLOGY CO-OPTIMIZATION FLOWS | PARIHAR, SUCHIN | — |
| 18415501 | ADAPTIVE AND INCREMENTAL CIRCUIT DESIGN IMPLEMENTATION | ALAWDI, ANWER AHMED | — |
| 18499021 | METRICS FOR INSTANCE RANKING FOR CLASSIFICATION AND REGRESSION | HOUNTON, AWADAGBE GERARD | — |
| 18141251 | ADJUSTMENTS TO SUPERCONDUCTING ELECTRONIC CIRCUIT DESIGNS USING PASSIVE TRANSMISSION LINE MODELING | KIM, EUNHEE | — |
Cases in front of an examiner whose interview lift is 10 percentage points or more — i.e. interviewed cases historically resolve more favorably than non-interviewed ones. The top 4 ordered by deadline are shown.
| App # | Title | Examiner | Due in |
|---|---|---|---|
| 18415501 | ADAPTIVE AND INCREMENTAL CIRCUIT DESIGN IMPLEMENTATION | ALAWDI, ANWER AHMED | — |
| 18560283 | METAL-INSULATOR-METAL CAPACITOR INSERTION | AISAKA, BRYCE M | — |
| 18141251 | ADJUSTMENTS TO SUPERCONDUCTING ELECTRONIC CIRCUIT DESIGNS USING PASSIVE TRANSMISSION LINE MODELING | KIM, EUNHEE | — |
| 18127376 | DYNAMIC CONTROL OF CIRCUIT DESIGN EMULATION | OCHOA, JUAN CARLOS | — |
| Client (Assignee) | Pending OAs |
|---|---|
| Synopsys, Inc. | 6 |
| Art Unit | Apps |
|---|---|
| 2126 | 1 |
| App # | Title | Client | Examiner | Art Unit | Statutes | Status | Due in | AI | Filed |
|---|---|---|---|---|---|---|---|---|---|
| 18590646 | POWER PERFORMANCE AREA OPTIMIZATION IN DESIGN TECHNOLOGY CO-OPTIMIZATION FLOWS | Synopsys, Inc. | PARIHAR, SUCHIN | §102§103 | Non-Final OA | — | Pending | Feb 28, 2024 | |
| 18415501 | ADAPTIVE AND INCREMENTAL CIRCUIT DESIGN IMPLEMENTATION | Synopsys, Inc. | ALAWDI, ANWER AHMED | §102§103 | Non-Final OA | — | Pending | Jan 17, 2024 | |
| 18560283 | METAL-INSULATOR-METAL CAPACITOR INSERTION | Synopsys, Inc. | AISAKA, BRYCE M | §112 | Non-Final OA | — | Pending | Nov 10, 2023 | |
| 18499021 | METRICS FOR INSTANCE RANKING FOR CLASSIFICATION AND REGRESSION | Synopsys, Inc. | HOUNTON, AWADAGBE GERARD | 2126 | §101§102§103 | Non-Final OA | — | Pending | Oct 31, 2023 |
| 18141251 | ADJUSTMENTS TO SUPERCONDUCTING ELECTRONIC CIRCUIT DESIGNS USING PASSIVE TRANSMISSION LINE MODELING | Synopsys, Inc. | KIM, EUNHEE | §101§103§112 | Non-Final OA | — | Pending | Apr 28, 2023 | |
| 18127376 | DYNAMIC CONTROL OF CIRCUIT DESIGN EMULATION | Synopsys, Inc. | OCHOA, JUAN CARLOS | §103 | Non-Final OA | — | Pending | Mar 28, 2023 |
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