5 pending office actions • 1 client • 5 examiners • 3 art units • 0 of 5 (0%) have an AI response strategy ready • 31 patents granted in the last 365 days
Based on the USPTO statutory response window for each pending office action. 3 of the docket's apps have a known mailing date; the rest are excluded from the tile counts.
Every pending office action with a known statutory deadline, placed on a days-until-due axis. Dots left of Today are overdue; the further right, the more runway. Cases that share a deadline window stack vertically. 3 of the docket's apps have a known mailing date.
Difficulty is derived from the rejection statutes on the most recent pending office action. §101-driven and multi-statute cases are graded Hard; §112-only and obviousness-type double-patenting cases are graded Easy; everything else is Medium. "Unknown" means we have not yet parsed a statute for that office action.
| Bucket | Cases |
|---|---|
| §103 only | 5 (100%) |
How the docket's pending cases split across USPTO tech-center bands.
Manual office-action response work runs about 10 hours per case. The time-saved bands below show what IP Author's prosecution pipeline typically delivers — a conservative 20% on the low end, 35% in the middle, 50% on the high end.
| Examiner | Apps on this docket | Allow rate | Interview lift |
|---|---|---|---|
| SAMLUK, JESSE PAUL | 1 | 47.4% | +45.9% |
| DINH, PAUL | 1 | 89.4% | +4.2% |
| AISAKA, BRYCE M | 1 | 87.3% | +10.5% |
| LIN, ARIC | 1 | 59.9% | +12.2% |
| HAO, YI | 1 | 34.8% | +43.3% |
Cases in front of an examiner with an allow rate of 80%+ where the difficulty is Easy or Medium. The top 2 ordered by deadline are shown.
| App # | Title | Examiner | Due in |
|---|---|---|---|
| 18137382 | CONSTANT, EQUAL, OR OPPOSITE REGISTERS OR PORTS DETECTION DURING LOGIC SYNTHESIS | AISAKA, BRYCE M | 16d overdue |
| 18215133 | FIELD-PROGRAMMABLE GATE ARRAY (FPGA) MODULAR IMPLEMENTATION | DINH, PAUL | — |
Cases in front of an examiner whose interview lift is 10 percentage points or more — i.e. interviewed cases historically resolve more favorably than non-interviewed ones. The top 4 ordered by deadline are shown.
| App # | Title | Examiner | Due in |
|---|---|---|---|
| 18137382 | CONSTANT, EQUAL, OR OPPOSITE REGISTERS OR PORTS DETECTION DURING LOGIC SYNTHESIS | AISAKA, BRYCE M | 16d overdue |
| 18071396 | PROCESS TO RELAY KNOWLEDGE AND GUIDE SYNTHESIS ALONGSIDE EARLY DETECTION OF LOGIC OPTIMIZATIONS | LIN, ARIC | 56d |
| 17845403 | SYNCHRONIZING DISTRIBUTED SIMULATIONS OF A CIRCUIT DESIGN | HAO, YI | 72d |
| 18653722 | MIXED-PRECISION NEURAL NETWORKS | SAMLUK, JESSE PAUL | — |
| Client (Assignee) | Pending OAs |
|---|---|
| Synopsys, Inc. | 5 |
| Art Unit | Apps |
|---|---|
| 2851 | 3 |
| 2411 | 1 |
| 2187 | 1 |
| App # | Title | Client | Examiner | Art Unit | Statutes | Status | Due in | AI | Filed |
|---|---|---|---|---|---|---|---|---|---|
| 18653722 | MIXED-PRECISION NEURAL NETWORKS | Synopsys, Inc. | SAMLUK, JESSE PAUL | 2411 | §103 | Final Rejection | — | Pending | May 02, 2024 |
| 18215133 | FIELD-PROGRAMMABLE GATE ARRAY (FPGA) MODULAR IMPLEMENTATION | Synopsys, Inc. | DINH, PAUL | 2851 | §103 | Non-Final OA | — | Pending | Jun 27, 2023 |
| 18137382 | CONSTANT, EQUAL, OR OPPOSITE REGISTERS OR PORTS DETECTION DURING LOGIC SYNTHESIS | Synopsys, Inc. | AISAKA, BRYCE M | 2851 | §103 | Final Rejection | 16d overdue | Pending | Apr 20, 2023 |
| 18071396 | PROCESS TO RELAY KNOWLEDGE AND GUIDE SYNTHESIS ALONGSIDE EARLY DETECTION OF LOGIC OPTIMIZATIONS | Synopsys, Inc. | LIN, ARIC | 2851 | §103 | Non-Final OA | 56d | Pending | Nov 29, 2022 |
| 17845403 | SYNCHRONIZING DISTRIBUTED SIMULATIONS OF A CIRCUIT DESIGN | Synopsys, Inc. | HAO, YI | 2187 | §103 | Non-Final OA | 72d | Pending | Jun 21, 2022 |
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