Prosecution Insights
Last updated: May 29, 2026

Wells St. John, P.S.

7 pending office actions • 1 client • 7 examiners • 5 art units • 0 of 7 (0%) have an AI response strategy ready • 75 patents granted in the last 365 days

Portfolio Summary

7
Total Pending OAs
4
Non-Final OAs
3
Final Rejections
0
Advisory / Quayle

Response Deadline Pressure

Based on the USPTO statutory response window for each pending office action. 7 of the docket's apps have a known mailing date; the rest are excluded from the tile counts.

1
Overdue
0
Due this week
4
Due this month
1
Due in next 60 days
1
Due later

Deadline Fire Line

Every pending office action with a known statutory deadline, placed on a days-until-due axis. Dots left of Today are overdue; the further right, the more runway. Cases that share a deadline window stack vertically. 7 of the docket's apps have a known mailing date.

-30dToday30d60d90d120d
Overdue (1)Due ≤ 30 days (4)Due ≤ 60 days (1)Due later (1)

Case Difficulty Mix

Difficulty is derived from the rejection statutes on the most recent pending office action. §101-driven and multi-statute cases are graded Hard; §112-only and obviousness-type double-patenting cases are graded Easy; everything else is Medium. "Unknown" means we have not yet parsed a statute for that office action.

0
Hard (0%)
6
Medium (86%)
1
Easy (14%)
0
Unknown (0%)

Rejection Statute Mix

BucketCases
§103 only6 (86%)
§112 only1 (14%)

Industry Mix

How the docket's pending cases split across USPTO tech-center bands.

0
Life Sciences
0% of docket
0
Information Tech
0% of docket
0
Communications
0% of docket
7
Semiconductors
100% of docket
0
Mechanical / Eng
0% of docket
0
Business / Other
0% of docket

Time-on-OA Estimate

Manual office-action response work runs about 10 hours per case. The time-saved bands below show what IP Author's prosecution pipeline typically delivers — a conservative 20% on the low end, 35% in the middle, 50% on the high end.

70 h
Manual time on pending OAs
14 h
Time saved (low, 20%)
24 h
Time saved (mid, 35%)
0.6 wks
FTE-weeks freed (mid)

Top Examiners on this docket

ExaminerApps on this docketAllow rateInterview lift
PARENDO, KEVIN A 1 71.9% +11.3%
WALL, VINCENT 1 61.8% +25.1%
KOO, LAMONT B 1 80.5% +4.9%
WEGNER, AARON MICHAEL 1 71.4% -2.2%
CIESLEWICZ, ANETA B 1 66.7% -1.8%
CHAMBLISS, ALONZO 1 90.0% -25.1%
GUPTA, RAJ R 1 68.1% +13.6%

Quick Wins (2)

Cases in front of an examiner with an allow rate of 80%+ where the difficulty is Easy or Medium. The top 2 ordered by deadline are shown.

App #TitleExaminerDue in
18533410 Integrated Assemblies and Semiconductor Memory Devices KOO, LAMONT B 22d
17747166 Memory Arrays Comprising Strings Of Memory Cells And Methods Used In Forming A Memory Array Comprising Strings Of Memory Cells CHAMBLISS, ALONZO 47d

Interview Candidates (3)

Cases in front of an examiner whose interview lift is 10 percentage points or more — i.e. interviewed cases historically resolve more favorably than non-interviewed ones. The top 3 ordered by deadline are shown.

App #TitleExaminerDue in
18620002 MEMORY ARRAY HAVING BRIDGING MATERIAL BETWEEN ADJACENT MEMORY BLOCKS PARENDO, KEVIN A 9d
18403266 Memory Circuitry And Method Used In Forming Memory Circuitry WALL, VINCENT 29d
17720032 Integrated Assemblies Having Semiconductor Oxide Channel Material, and Methods of Forming Integrated Assemblies GUPTA, RAJ R 70d

Client Portfolio (1 client)

Client (Assignee)Pending OAs
Micron 7

Top Art Units

Art UnitApps
28972
28932
28961
28981
28131

Pending Office Actions

App #TitleClientExaminerArt UnitStatutesStatusDue inAIFiled
18620002 MEMORY ARRAY HAVING BRIDGING MATERIAL BETWEEN ADJACENT MEMORY BLOCKS Micron Technology, Inc. PARENDO, KEVIN A 2896 §112 Non-Final OA 9d Pending Mar 28, 2024
18403266 Memory Circuitry And Method Used In Forming Memory Circuitry Micron Technology, Inc. WALL, VINCENT 2898 §103 Non-Final OA 29d Pending Jan 03, 2024
18533410 Integrated Assemblies and Semiconductor Memory Devices Micron Technology, Inc. KOO, LAMONT B 2813 §103 Non-Final OA 22d Pending Dec 08, 2023
17893436 Memory Circuitry And Method Used In Forming Memory Circuitry Micron Technology, Inc. WEGNER, AARON MICHAEL 2897 §103 Final Rejection 28d Pending Aug 23, 2022
17883241 Integrated Memory Comprising Gated Regions Between Charge-Storage Devices and Access Devices Micron Technology, Inc. CIESLEWICZ, ANETA B 2893 §103 Final Rejection 3d overdue Pending Aug 08, 2022
17747166 Memory Arrays Comprising Strings Of Memory Cells And Methods Used In Forming A Memory Array Comprising Strings Of Memory Cells Micron Technology, Inc. CHAMBLISS, ALONZO 2897 §103 Non-Final OA 47d Pending May 18, 2022
17720032 Integrated Assemblies Having Semiconductor Oxide Channel Material, and Methods of Forming Integrated Assemblies Micron Technology, Inc. GUPTA, RAJ R 2893 §103 Final Rejection 70d Pending Apr 13, 2022

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